Interface test adapter for actively testing an integrated circuit chip package

• US 5,896,037 A
• Filed: 10/10/1996
• Issued: 04/20/1999
• Est. Priority Date: 10/10/1996
• Status: Expired due to Fees

• Current Assignee: Methode Electronics Incorporated
• Original Assignee: Methode Electronics Incorporated
• Inventors: Chang, Luke, Kudla, James M.
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/728,886
• Time in Patent Office: 922 Days
• Field of Search: 324/754, 324/755, 324/763, 324/765, 439/65-85
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass

Abstract

A Test Adapter for actively testing chip package such as a ball grid array in operation with a printed circuit board are disclosed. The test adapter provides accessible test points for monitoring input and output signals of an operating chip package. The adapter includes an interface adapter board having a plurality of contact pads disposed on its surface, in a pattern corresponding to the footprint of the chip package. A plurality of contact terminals protrude from the bottom of the interface adapter board and are connected to the contact pads on the upper surface, and are configured to engage a receiving socket mounted to a printed circuit board. A plurality of test pins are also connected to the contact pins such that test probes can be connected to the test pins and the input/output signals associated with the chip package can be monitored by the probes.

Claims

1. A test adapter for providing accessible test points for actively monitoring multiple input and output signals of a ball grid array integrated circuit chip package, said adapter comprising:

a BGA pin header for passing input/output signals between said grid array (BGA) integrated circuit chip package and printed circuit board, said BGA pin header having an array of pads for receiving said balls of said ball grid array integrated circuit chip package and an array of pins for communication of said input/output signals with said printed cicuit board, said BGA pin header thereby converting input/output signals communicated on balls on said ball grid array integrated circuit chip package to an array of pins communicating said input/output signals;

a pin grid array socket for receiving said pins from said BGA pin header and providing said input/output signals on an array of contact tails, said tails for bonding to a interface adapter board;

an interface adapter board for mounting said grid array (BGA) integrated circuit chip package to said printed circuit board for communicating said input and output signals to and from said ball grid array integrated circuit chip package;

a plurality of test contacts located at the periphery of said interface adapter board whereby said input and output signals are conveyed between said ball grid array integrated circuit chip package and said printed circuit board, and can be actively monitored from said test contacts;

a plurality of contact pads disposed on a first surface of said interface adapter board, and arranged to send and receive said input and output signals;

a plurality of output contacts disposed on a second surface of said interface adapter board being arranged to mount on a printed circuit board in place of said chip package, each said output contact being electrically connected to one said contact pad;

a plurality of test contacts wherein each test contact is electrically connected to one said contact pad; and

whereby said input and output signals are conveyed between said ball grid array integrated circuit chip package and said printed circuit board, and can be actively monitored from said test contacts.

2. The test adapter of claim 1 further comprising custom means for matching a footprint of the interface adapter board to the footprint of said ball grid array (BGA) integrated circuit chip package under test.

3. The adapter of claim 1 wherein said test contacts comprise contact pins protruding from said interface adapter board and having a one to one correspondence with the footprint of the ball grid array (BGA) integrated circuit chip package.

4. The adapter of claim 3 further comprising custom means for matching a footprint of the interface adapter board to the footprint of said ball grid array (BGA) integrated circuit chip package under test, said custom means including

a second pin grid array socket, for electrical connection at the second side of said interface adapter board, for providing said input/output signals;

a custom pin header for communicating input/output signals to and from said second pin grid array socket for providing those signals to and from the printed circuit board on a number of balls less then the entire number of contacts provided by said integrated circuit adapter board for the footprint of said ball grid array (BGA) integrated circuit chip package under test.

5. The adapter of claim 4 wherein said test contacts pins are arranged as a plurality of ribbon cable headers.

6. The adapter of claim 4 wherein said test contact pins are arranged in at least one grid array.

7. The adapter of claim 1 wherein said test contacts are mounted to a separate test header board, and one of a flexible cable and flexible printed circuitry, provides the electrical connection between said interface adapter board and said test header board.

8. The adapter of claim 7 wherein the connections between said input and output signals and said test contacts are programmable such that any one input or output signal can be monitored from any one of said test contacts.