DPSK demodulator which may be used in an interrogator of a remote intelligence communication system

• US 5,896,060 A
• Filed: 07/15/1997
• Issued: 04/20/1999
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovard, David K., Pax, George E.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/893,368
• Time in Patent Office: 644 Days
• Field of Search: 329/304-310, 375/324-328, 375/329-333
• US Class Current: 329/304
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

A differentially phase shift keyed demodulator for use in an interrogator of a remote intelligent communication system. The demodulator includes a quadrature combiner delaying one of the quadrature signals and thereafter combining the delayed and undelayed signals along with a FIR matched filter, which filters the combiner output whereby the differentially phase shift keyed data on a sub-carrier can be demodulated using a simple delay and multiplying scheme in response to the filtered output.

Claims

1. A differential phase shift keyed demodulator which utilizes quadrature input signals that are supplied to and converted to quadrature digital outputs by analog to digital converters, comprising:

a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals;

a finite impulse response matched filter coupled to the quadrature combiner for filtering the combined output signals; and

a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal.

2. A demodulator as in claim 1 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub-carrier.

3. A demodulator as in claim 1 wherein the FIR matched filter has a square time envelope.

4. A demodulator as in claim 2 wherein the FIR matched filter has a square time envelope and taps at the sub-carrier frequency.

5. A demodulator as in claim 2 wherein the multiplier circuit generates a two times the sub-carrier frequency signal.

6. A demodulator as in claim 5 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub-carrier frequency signal.

7. A demodulator as in claim 1 further including a synchronization circuit of recovering a data clock from the demodulated output signal.

8. In a remote intelligent communication system including a programmable computer and a plurality of remote communication devices connected to the computer via an interrogator and a communications medium, said interrogator including a differential phase shift keyed demodulator which utilizes quadrature input signals that are supplied to and converted to quadrature digital outputs by analog to digital converters, a differential phase shift keyed demodulator comprising:

a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals;

a finite impulse response matched filter coupled to the quadrature combiner for filtering the combined output signals, and

a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal.

9. A system as in claim 8 wherein the remote communication devices are transducers which produce backscatter signals and the system further includes a downconverter for producing said quadrature input signals.

10. A system as in claim 9 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub-carrier.

11. A system as in claim 9 wherein the quadrature input signals are filtered prior to being input to the analog to digital converters.

12. A system as in claim 8 wherein the FIR matched filter has a square time envelope.

13. A system as in claim 9 wherein the FIR matched filter has a square time envelope and has taps at the sub-carrier frequency.

14. A system as in claim 9 wherein the multiplier circuit generates a two times the sub-carrier frequency signal.

15. A system as in claim 14 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub-carrier frequency signal.

16. A system as in claim 8 further including a synchronization circuit for recovering a data clock from the demodulated output signal.