Direct memory access controller with full read/write capability

• US 5,896,550 A
• Filed: 04/03/1997
• Issued: 04/20/1999
• Est. Priority Date: 04/03/1997
• Status: Expired due to Term

• Current Assignee: Complex Memory LLC (IPValuation Partners, LLC)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Wehunt, Omer Lem, Lavin, Jeffrey M.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Hossain, Abu
• Application Number:
  US08/825,661
• Time in Patent Office: 747 Days
• Field of Search: 395/842, 395/845, 395/843, 395/846, 395/281, 395/823, 395/325, 395/497.01, 711/100, 711/104, 711/105
• US Class Current: 710/26
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Versatility of access to a register set within a direct memory access (DMA) controller is increased. The DMA controller controls direct memory access transfers to and from a main memory. When a first control field in a configuration register has a first value, normal operating access is provided to a register set within the DMA controller. The register set provides control and status of the direct memory access transfers to and from the main memory. When the first control field in the configuration register has a second value special access is provided to the register set. The special access allows storage and restoration of a state of a DMA transfer.

Claims

1. A method for increasing versatility of access to a register set within a direct memory access (DMA) controller, the DMA controller controlling direct memory access transfers to and from a main memory, the method comprising the following steps:

(a) when a first control field in a configuration register has a first value, providing normal operating access to a register set within the DMA controller, wherein the normal operating access includes the register set providing control and status of the direct memory access transfers to and from the main memory, the normal operating access not allowing storage and restoration of a state of a DMA transfer; and

,

(b) when the first control field in the configuration register has a second value, providing special access to the register set, the special access allowing storage and restoration of a state of a DMA transfer.

2. A method as in claim 1 wherein step (b) includes:

providing access to each register in the register set through placing a predetermined index into an address register and performing a transfer of data to/from a data values register.

3. A method as in claim 1 wherein in step (b) access to each register in the set of registers is an inverted operating access, wherein for registers in the set of register:

registers that for normal operating access are read only become in inverted operating access write only;

registers that for normal operating access are write only become in inverted operating access read only;

registers that for normal operating access are both read and write accessible remain in inverted operating access read and write accessible; and

,

registers that for normal operating access are writeable only when linked with a write to another register become in inverted operating access writeable independent of any other register.

4. A method as in claim 1 wherein step (a) includes:

providing write only access to a base address register;

providing read access and providing write access to a current address register wherein write access is permitted to the current address register only when written to simultaneously with a write to the base address register;

providing write only access to a base word count register; and

,

providing read access and providing write access to a current word count register wherein write access is permitted to the current word count register only when written to simultaneously with a write to the base word count register.

5. A method as in claim 4 wherein in step (b) includes:

providing access to the base address register, the current address register, the base word count register and the current word count register through placing an associated index into an address register and performing a transfer of data to/from a data values register.

6. A method as in claim 4 wherein in step (b) access to each register in the set of registers is an inverted operating access, so that step (b) includes:

providing read only access to the base address register;

providing write access to the current address register independent of a write to the base address register;

providing read only access to the base word count register; and

, providing write access to the current word count register independent of a write to the base word count register.

7. A computing system comprising:

a bus;

a main memory coupled to the bus;

a central processing unit, coupled to the bus; and

,

a direct memory access (DMA) controller, coupled to the bus, the DMA controller controlling direct memory access transfers to and from the main memory, the DMA controller including;

a register set for providing control and status of the direct memory access transfers to and from the main memory, limited access being provided to registers within the register set, and

a configuration register having a first control field, wherein access provided to registers within the register set changes based on a value placed in the first control field.

8. A computing system as in claim 7 wherein the direct memory access controller additionally comprises:

an address register; and

,

a data values register;

wherein when the first control field is at a first value, each register in the register set is available by placing a predetermined index into the address register and performing a transfer of data to/from the data values register.

9. A computing system as in claim 7 wherein when the first control field is at a first value, access to each register in a register set is a normal operating access, and wherein when the first control field is at a second value, access to each register in a register set is an inverted operating access, wherein:

registers that for normal operating access are read only become in inverted operating access write only;

registers that for normal operating access are write only become in inverted operating access read only;

registers that for normal operating access are both read and write accessible remain in inverted operating access read and write accessible; and

registers that for normal operating access are writeable only when linked with a write to another register become in inverted operating access writeable independent of any other register.

10. A computing system as in claim 7 wherein the register set includes:

a base address register which in a normal operating access is write only accessible;

a current address register which in the normal operating access is read accessible, and is write accessible when written to simultaneously with a write to the base address register;

a base word count register which in the normal operating access is write only accessible; and

,

a current word count register which in the normal operating access is read accessible, and is write accessible when written to simultaneously with a write to the base word count register.

11. A computing system as in claim 10, wherein the direct memory access controller additionally comprises:

an address register; and

,

a data values register;

wherein when the first control field is at a first value, read and write access are available to the base address register, the current address register, the base word count register and the current word count register by placing an associated index into the address register and performing a transfer of data to the data values register.

12. A computing system as in claim 10 wherein when the first control field is at a first value, access to each register in a register set is a normal operating access, and wherein when the first control field is at a second value, access to each register in a register set is an inverted operating access, wherein for the inverted operating access:

the base address register is read only accessible;

the current address register is write accessible when written to independent of a write to the base address register;

the base word count register is read only accessible; and

, the current word count register is write accessible, when written to independent of a write to the base word count register.

13. A computing system as in claim 10 wherein the register set additionally includes:

a status register which in a normal operating access is read only accessible;

a command register which in the normal operating access is write only accessible; and

,

a request register which in the normal operating access is write only accessible.

14. A direct memory access (DMA) controller, the DMA controller controlling direct memory access transfers to and from a main memory, the DMA controller comprising:

a register set for providing control and status of the direct memory access transfers to and from the main memory, limited access being provided to registers within the register set; and

,

a configuration register having a first control field, wherein access provided to registers within the register set changes based on a value placed in the first control field.

15. A direct memory access controller as in claim 14 additionally comprising:

an address register; and

,

a data values register;

wherein when the first control field is at a first value, each register in the register set is available by placing a predetermined index into the address register and performing a transfer of data to/from the data values register.

16. A direct memory access controller as in claim 14 wherein when the first control field is at a first value, access to each register in a register set is a normal operating access, and wherein when the first control field is at a second value, access to each register in a register set is an inverted operating access, wherein:

registers that for normal operating access are read only become in inverted operating access write only;

registers that for normal operating access are write only become in inverted operating access read only;

registers that for normal operating access are both read and write accessible remain in inverted operating access read and write accessible; and

,

registers that for normal operating access are writeable only when linked with a write to another register become in inverted operating access writeable independent of any other register.

17. A direct memory access controller as in claim 14 wherein the register set includes:

a base address register which in a normal operating access is write only accessible;

a current address register which in the normal operating access is read accessible, and is write accessible when written to simultaneously with a write to the base address register;

a base word count register which in the normal operating access is write only accessible; and

,

a current word count register which in the normal operating access is read accessible, and is write accessible when written to simultaneously with a write to the base word count register.

18. A direct memory access controller as in claim 17 additionally comprising:

an address register; and

,

a data values register;

wherein when the first control field is at a first value, read and write access are available to the base address register, the current address register, the base word count register and the current word count register by placing an associated index into the address register and performing a transfer of data to the data values register.

19. A direct memory access controller as in claim 17 wherein when the first control field is at a first value, access to each register in a register set is a normal operating access, and wherein when the first control field is at a second value, access to each register in a register set is an inverted operating access, wherein for the inverted operating access:

the base address register is read only accessible;

the current address register is write accessible when written to independent of a write to the base address register;

the base word count register is read only accessible; and

, the current word count register is write accessible, when written to independent of a write to the base word count register.

20. A direct memory access controller as in claim 17 wherein the register set includes:

a status register which in a normal operating access is read only accessible;

a command register which in the normal operating access is write only accessible; and

,

a request register which in the normal operating access is write only accessible.