Microprocessor employing local caches for functional units to store memory operands used by the functional units

• US 5,898,849 A
• Filed: 04/04/1997
• Issued: 04/27/1999
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tran, Thang M.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/835,066
• Time in Patent Office: 753 Days
• Field of Search: 711/119, 711/121, 711/138, 395/392, 395/393, 395/395, 395/379, 395/800.32
• US Class Current: 712/203
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A microprocessor employs a local cache for each functional unit, located physically close to that functional unit. The local caches are relatively small as compared to a central cache optionally included in the microprocessor as well. Because the local caches are small, internal interconnection delays within the local caches may be less than those experienced by the central cache. Additionally, the physical proximity of the local cache to the functional unit which accesses the local cache reduces the interconnect delay between the local cache and the functional unit. If the memory operand hits in a remote cache (either a different local cache or the central cache), the cache line containing the memory operand is transferred to the local cache experiencing the miss. According to one embodiment including multiple symmetrical functional units, the local caches coupled to the symmetrical functional units are restricted to storing different cache lines from each other. For example, a number of bits of the tag address may be used to select which of the local caches is to store the corresponding cache line. A data prediction scheme for predicting the functional unit to which a given instruction should be dispatched may be implemented, wherein the prediction is formed based upon the cache line storing the memory operand during a previous execution of the given instruction.

Claims

1. A microprocessor comprising:

a first functional unit configured to execute instructions, wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction, is configured to generate a first memory address corresponding to a first memory operand of said first instruction;

a second functional unit configured to execute instructions, wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, is configured to generate a second memory address corresponding to a second memory operand of said second instruction;

a first local cache coupled to said first functional unit, wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and

a second local cache coupled to said second functional unit, wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction.

2. The microprocessor as recited in claim 1 further comprising a global tags and control unit coupled to said first local cache and said second local cache, wherein said global tags and control unit is configured to store a set of tags corresponding to cache lines stored in said first local cache and said second local cache, and wherein said global tags and control unit is further configured to determine, responsive to said set of tags, if said first memory operand hits in said first local cache and to determine, responsive to said set of tags, if said second memory operand hits in said second local cache.

3. The microprocessor as recited in claim 2 wherein said global tags and control unit is further configured to determine if said first memory operand hits in said second local cache if said first memory operand misses said first local cache.

4. The microprocessor as recited in claim 3 wherein, upon determining that said first memory operand hits in said second local cache, said global tags and control unit is further configured to transfer a first cache line containing said first operand from said second local cache to said first local cache.

5. The microprocessor as recited in claim 4 wherein said global tags and control unit is further configured to invalidate said first cache line in said second local cache upon transferring said first cache line to said first local cache.

6. The microprocessor as recited in claim 2 further comprising a data cache coupled to said global tags and control unit, said data cache having a substantially larger capacity than said first local cache and said second local cache.

7. The microprocessor as recited in claim 6 wherein said global tags and control unit is further configured to determine if said first memory operand hits in said data cache upon determining that said first memory operand misses said first local cache.

8. The microprocessor as recited in claim 7 wherein said global tags and control unit is further configured to transfer a first cache line containing said first memory operand to said first local cache if said first memory operand hits in said data cache.

9. The microprocessor as recited in claim 8 wherein said global tags and control unit is further configured to invalidate said first cache line from said data cache upon transferring said first cache line to said first local control unit.

10. The microprocessor as recited in claim 7 wherein said global tags and control unit is configured to initiate a fetch of said first memory operand from a main memory subsystem upon detecting a miss of said first memory operand in said data cache, and to transfer a first cache line including said first memory operand into said first local cache upon receiving said first cache line from said main memory subsystem.

11. The microprocessor as recited in claim 10 wherein said global tags and control unit is further configured to transfer a second cache line displaced from said first local cache by said first cache line into said data cache.

12. The microprocessor as recited in claim 1 wherein said first functional unit comprises an integer unit configured to execute integer instructions.

13. The microprocessor as recited in claim 1 wherein said first functional unit comprises a floating point unit configured to execute floating point instructions.

14. The microprocessor as recited in claim 1 wherein said first functional unit comprises a multimedia unit configured to execute multimedia instructions.

15. The microprocessor as recited in claim 1 wherein said first local cache is configured to store a first set of tags corresponding to cache lines stored within said first local cache, and wherein said first local cache is configured to determine if said first memory operand is stored therein by examining said first set of tags, and wherein said second local cache is configured to store a second set of tags corresponding to cache lines stored within said second local cache, and wherein said second local cache is configured to determine if said second memory operand is stored therein by examining said second set of tags.

16. The microprocessor as recited in claim 2 wherein said set of tags includes a location field for each cache line, said location field identifying which one of a plurality of caches including said first local cache and said second local cache is storing said cache line.

17. A method for accessing memory operands in a microprocessor, the method comprising:

generating a first address corresponding to a first memory operand of a first instruction in a first functional unit of said microprocessor responsive to a first plurality of address operands specified by said first instruction;

generating a second address corresponding to a second memory operand of a second instruction in a second functional unit responsive to a second plurality of address operands specified by said second instruction;

accessing a first local cache coupled to said first functional unit with said first address in order to locate said first memory operand; and

accessing a second local cache coupled to said second functional unit with said second address in order to locate said second memory operand.

18. A computer system comprising:

a microprocessor including;

a first functional unit configured to execute instructions, wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction, is configured to generate a first memory address corresponding to a first memory operand of said first instruction;

a second functional unit configured to execute instructions, wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, is configured to generate a second memory address corresponding to a second memory operand of said second instruction;

a first local cache coupled to said first functional unit, wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and

a second local cache coupled to said second functional unit, wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction; and

an input/output (I/O) device coupled to said microprocessor and to another computer system, wherein said I/O device is configured to communicate between said computer system and said another computer system.

19. The computer system as recited in claim 18 wherein said I/O device comprises a modem.

20. A computer system comprising:

a microprocessor including;

a first functional unit configured to execute instructions;

a second functional unit configured to execute instructions;

a first local cache coupled to said first functional unit, wherein said first functional unit is configured to access said first local cache in order to retrieve a first memory operand corresponding to a first instruction;

a second local cache coupled to said second functional unit, wherein said second functional unit is configured to access said second local cache in order to retrieve a second memory operand corresponding to a second instruction; and

a global tags and control unit coupled to said first local cache and said second local cache, wherein said global tags and control unit is configured select one of said first local cache and said second local cache to store a particular cache line in response to a particular address corresponding to said particular cache line; and

an input/output (I/O) device coupled to said microprocessor and to another computer system, wherein said I/O device is configured to communicate between said computer system and said another computer system.

21. The computer system as recited in claim 20 wherein said I/O device comprises a modem.

22. A method for dispatching an instruction to one of a first functional unit configured to execute said instruction and a second functional unit configured to execute said instruction, said first functional unit being coupled to a first local cache configured to store memory operands and said second functional unit being coupled to a second local cache configured to store memory operands, the method comprising:

storing a particular memory operand into one of said first local cache and said second local cache responsive to one or more bits of a corresponding memory address of said particular memory operand;

predicting which one of said first local cache and said second local cache is storing a first memory operand corresponding to said instruction;

dispatching said instruction to said first functional unit if said first local cache is predicted; and

dispatching said instruction to said second functional unit if said second local cache is predicted.

23. The method as recited in claim 22 wherein said predicting comprises recording an indication of which one of said first local cache and said second local cache stores said first memory operand upon a previous execution of said instruction.

24. The method as recited in claim 23 further comprising updating said indication if said predicting is incorrect.

25. A microprocessor comprising:

a first functional unit configured to execute instructions;

a second functional unit configured to execute instructions;

a first local cache coupled to said first functional unit, wherein said first functional unit is configured to access said first local cache in order to retrieve a first memory operand corresponding to a first instruction;

a second local cache coupled to said second functional unit, wherein said second functional unit is configured to access said second local cache in order to retrieve a second memory operand corresponding to a second instruction; and

a global tags and control unit coupled to said first local cache and said second local cache, wherein said global tags and control unit is configured select one of said first local cache and said second local cache to store a particular cache line in response to a particular address corresponding to said particular cache line.

26. The microprocessor as recited in claim 25 further comprising a decode unit configured to dispatch a first instruction to said first functional unit if a first address corresponding to a first memory operand accessed by said first instruction during a prior execution of said first instruction is an address which said global tags and control unit is configured to store into said first local cache.

27. The microprocessor as recited in claim 26 wherein said global tags and control unit, upon detecting a hit in said second local cache of a second memory operand accessed by said first instruction, is configured to forward said second memory operand to said first functional unit.

28. The microprocessor as recited in claim 27 wherein said decode unit, upon a subsequent dispatch of said first instruction, is configured to dispatch said first instruction to said second functional unit.