Microprocessor employing local caches for functional units to store memory operands used by the functional units

  • US 5,898,849 A
  • Filed: 04/04/1997
  • Issued: 04/27/1999
  • Est. Priority Date: 04/04/1997
  • Status: Expired due to Term
First Claim
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1. A microprocessor comprising:

  • a first functional unit configured to execute instructions, wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction, is configured to generate a first memory address corresponding to a first memory operand of said first instruction;

    a second functional unit configured to execute instructions, wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, is configured to generate a second memory address corresponding to a second memory operand of said second instruction;

    a first local cache coupled to said first functional unit, wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and

    a second local cache coupled to said second functional unit, wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction.

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