First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache
First Claim
1. An integrated circuit first-in, first-out memory device comprising:
- an input bus for receiving data to be written to said memory device;
an input buffer coupled to said input bus for storing said data;
a dynamic random access memory array comprising a plurality of memory banks coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer;
a plurality of memory caches each of said memory caches corresponding to one of said plurality of memory banks;
an output bus coupled to said memory array, said plurality of memory caches and a read pointer for providing previously written data from said memory array to a corresponding one of said plurality of memory caches at a location indicated by said read pointer.
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Accused Products
Abstract
An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.
47 Citations
36 Claims
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1. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; a dynamic random access memory array comprising a plurality of memory banks coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; a plurality of memory caches each of said memory caches corresponding to one of said plurality of memory banks; an output bus coupled to said memory array, said plurality of memory caches and a read pointer for providing previously written data from said memory array to a corresponding one of said plurality of memory caches at a location indicated by said read pointer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for accessing a first-in, first-out memory device including a dynamic random access memory array and an associated static random access memory cache, said method comprising the steps of:
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determining a next write location within said memory array to which input data is to be written; writing said input data to said next write location within said memory array; further determining a next read location within said memory array from which previously written data is to be read; loading said previously written data from said memory array to said memory cache; reading said previously written data from said memory cache; and refreshing portions of said memory array during said step of reading. - View Dependent Claims (18, 19, 20, 21)
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22. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and an input multiplexer coupling said input bus to said input buffer. - View Dependent Claims (23, 24, 25, 26, 27)
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28. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and a write multiplexer counter for indicating a next column in said memory array to which data is to be written.
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29. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and a read multiplexer counter for indicating a next column in said memory array from which data is to be read.
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30. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and a maximum access time timer for indicating to said memory device that a precharge operation must be performed to said memory array.
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31. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and a refresh timer for indicating to said memory device that a refresh operation must be performed to said memory array.
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32. An integrated circuit first-in, first-out memory device comprising:
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an input bus for receiving data to be written to said memory device; an input buffer coupled to said input bus for storing said data; at least one dynamic random access memory array coupled to said input buffer and a write pointer for storing said data in said input buffer to a location within said memory array indicated by said write pointer; an output bus coupled to said memory array and a read pointer for providing previously written data from said memory array at a location indicated by said read pointer; and a memory not ready indicator for indicating to said memory device that said memory array is not currently accessible.
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33. A method for accessing a first-in, first-out memory device including a dynamic random access memory array and an associated static random access memory cache, said method comprising the steps of:
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determining a next write location within said memory array to which input data is to be written; writing said input data to said next write location within said memory array; further determining a next read location within said memory array from which previously written data is to be read; loading said previously written data from said memory array to said memory cache; reading said previously written data from said memory cache; and precharging bit lines of portions of said memory array during said step of reading. - View Dependent Claims (34)
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35. A method for accessing a first-in, first-out memory device including a dynamic random access memory array and an associated static random access memory cache, said method comprising the steps of:
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determining a next write location within said memory array to which input data is to be written; writing said input data to said next write location within said memory array; further determining a next read location with in said memory array from which previously written data is to be read; loading said previously written data from said memory array to said memory cache; reading said previously written data from said memory cache; and also writing said input data to said memory cache if said previously written data from said memory array in said memory cache corresponds to said next write location within said memory array to which said input data is to be written. - View Dependent Claims (36)
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Specification