Mixer device with image frequency rejection

• US 5,901,349 A
• Filed: 12/11/1996
• Issued: 05/04/1999
• Est. Priority Date: 12/15/1995
• Status: Expired due to Fees

• Current Assignee: EADS Secure Networks
• Original Assignee: Matra Communication
• Inventors: Robbe, Michel, Guegnaud, Herve
• Primary Examiner(s): Vo, Nguyen
• Assistant Examiner(s): Kincaid, Lester G.
• Application Number:
  US08/764,635
• Time in Patent Office: 874 Days
• Field of Search: 455/285, 455/293, 455/295, 455/296, 455/302, 455/303, 455/304, 455/305, 455/306, 455/313, 455/314, 455/324, 455/209, 455/280, 455/283, 455/288, 455/291, 455/292, 375/269, 375/279, 375/272, 375/316, 375/322, 375/324, 375/334, 329/323, 329/324, 329/346
• US Class Current: 455/302
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence

Abstract

The device forms first and second signals by mixing the input radio signal with two respective quadrature waves of frequency f_O. An algebraic sum of these two signals is phase-shifted by ±45° or ±135° at an intermediate frequency f_I. An output signal is formed by an algebraic sum between the phase-shifted signal and the first or second signal, in such a way that, at the intermediate frequency f_I, the output signal has a phase representative of that possessed by the input radio signal at a communication frequency f_C of the form f_O -f_I or f_O +f_I, with rejection of the phase of the input radio signal at the image frequency 2f_O -f_C.

Claims

1. Mixer device with image frequency rejection, comprising:

mixing means for forming a first signal by mixing an input radio signal with a first wave of frequency fO delivered by a local oscillator and a second signal by mixing the input radio signal with a second wave of frequency f_O delivered by the local oscillator and having a phase lag of 90°

with respect to said first wave;

means of algebraic summation of third and fourth mutually phase-shifted signals obtained from said first and second signals, in order to produce an output signal possessing, at an intermediate frequency f_I, a phase representative of a phase possessed by the input radio signal at a communication frequency f_C of the form f_O -f_I or f_O +f_I, with rejection of the phase possessed by the input radio signal at an image frequency 2f_O -f_C ;

phase-shifter means producing said third signal by filtering an algebraic sum of the first and second signals with a transfer function A(f); and

means for producing said fourth signal by applying to one of said first and second signals a transfer function B(f) such that, at the intermediate frequency f_I, the ratio A(f_I)/B(f_I) has modulus 1/√

2 and argument ±

45°

or ±

135°

.

2. Device according to claim 1, wherein the communication frequency f_C is equal to f_O -f_I, and wherein the means of algebraic summation and the phase-shifter means are arranged so as to produce an output signal which, at the intermediate frequency f_I, is the real part of a complex signal proportional to (X1+X2)e^-jπ

/4 /√

2-X1, to (X2-X1)e^jπ

/4 /√

2+X1, to (X1+X2)e^jπ

/4 /√

2-X2 or to (X2-X1)e^-jπ

/4 /√

2-X2, X1 and X2 respectively denoting said first and second signals.

3. Device according to claim 1, wherein the communication frequency f_C is equal to f₀ +f₁, and wherein the means of algebraic summation and the phase-shifter means are arranged so as to produce an output signal which, at the intermediate frequency f_I, is the real part of a complex signal proportional to (X1+X2)e^-jπ

/4 /√

2-X2, to (X1-X2)e^jπ

/4 /√

2+X2, to (X1+X2)e^jπ

/4 /√

2-X1 or to (X1-X2)e^-jπ

/4 /√

2-X1, X1 and X2 respectively denoting said first and second signals.

4. Device according to claim 1, wherein the phase-shifter means comprise at least one RC filter without floating capacitance.

5. Device according to claim 4, wherein the RC filter comprises a first resistor and a capacitor which are connected in parallel between a first terminal to which a constant voltage is applied and a second terminal, and wherein two currents respectively representing said first and second signals are injected at said second terminal, the voltage present at said second terminal constituting said third signal delivered to the means of algebraic summation.

6. Device according to claim 5, further comprising a second resistor with ohmic value substantially equal to that of said first resistor, connected between said first terminal and a third terminal, and wherein a current representing said first signal or said second signal is injected at said third terminal, the voltage present at said third terminal constituting said fourth signal delivered to the means of algebraic summation.

7. Device according to claim 6, wherein the first and second resistors are substantially identical variable resistors whose ohmic value R is slaved so as to satisfy the relation 2π

RCf_I =1, where C is the capacitance of said capacitor.

8. Device according to claim 7, further comprising a circuit for slaving said variable resistors comprising two cascaded RC filters, each including a capacitor of capacitance C.f_I /f₁ in parallel with a variable resistor which is substantially identical to said first and second resistors, a sinusoidal wave of frequency f₁ of the same order as the intermediate frequency f_I being applied to the two cascaded RC filters, the slaving circuit further including a multiplier receiving, on the one hand, said wave phase-shifted by the cascaded RC filters and, on the other hand, a non-phase-shifted version of said wave, and a low-pass filter receiving the output signal from the multiplier and having an output which adjusts the ohmic value of said variable resistors.

9. Device according to claim 4, wherein the mixing means comprise a first Gilbert cell yielding first and second currents whose difference represents the first signal, and a second Gilbert cell yielding third and fourth currents whose difference represents the second signal, wherein the phase-shifter means comprise first and second substantially identical resistors and first and second substantially identical capacitors, the first resistor and the first capacitor being mounted in parallel between a first terminal, to which a constant voltage is applied, and a second terminal, and the second resistor and the second capacitor being mounted in parallel between said first terminal and a third terminal, wherein the first and third currents are injected at said second terminal, whilst the second and fourth currents are injected at said third terminal, the difference between the voltage present at the third terminal and the voltage present at the second terminal representing said third signal, the device further including third and fourth substantially identical resistors, the third resistor being mounted between said first terminal and a fourth terminal, and the fourth resistor being mounted between said first terminal and a fifth terminal, and wherein the first and second currents or the third and fourth currents are respectively injected at said fourth terminal and at said fifth terminal, the difference between the voltage present at the fifth terminal and the voltage present at the fourth terminal representing said fourth signal.

10. Device according to claim 9, further comprising first, second, third and fourth bipolar transistors having respective bases at a constant voltage, the first and third currents being injected at the second terminal by way of the first bipolar transistor, the second and fourth currents being injected at the third terminal by way of the second bipolar transistor, the first current or the third current being injected at the fourth terminal by way of the third bipolar transistor, and the second current or the fourth current being injected at said fifth terminal by way of the fourth bipolar transistor.

11. Device according to claim 10, wherein the first, second, third and fourth resistors are sized in such a way that the ratio between an ohmic value of the third and fourth resistors and an ohmic value of the first and second resistors is 1-C_p /C_O, where C_O denotes the capacitance of the first and second capacitors, and C_p denotes a stray capacitance present between the first terminal and each of the second, third, fourth and fifth terminals due to the bipolar transistors.

12. Device according to claim 11, wherein the first, second, third and fourth resistors are variable resistors slaved so that the ohmic value of the first and second resistors is R_O =1/ 2π

(C_O -C_p) f_I ! and that the ohmic value of the third and fourth resistors is R₁ =1/(2π

C_O f_I).

13. Device according to claim 12, wherein said variable resistors consist of channels of respective MOS transistors having respective gates which receive an adjustment voltage.

14. Device according to claim 12, further comprising a circuit for slaving said variable resistors comprising two cascaded RC filters, each including a capacitor of capacitance CO.f_I /f.sub.₁, in parallel with a variable resistor which is substantially identical to said first and second variable resistors between said first terminal and an output of said RC filter, a sinusoidal wave of frequency f₁ of the same order as the intermediate frequency f_I being applied to the two cascaded RC filters, the slaving circuit further including two cells each including a variable resistor which is substantially identical to said third and fourth variable resistors and is connected between said first terminal and an output of said cell, the wave of frequency f₁ being also applied to the two cascaded cells, and wherein the slaving circuit comprises a multiplier receiving two signals arising respectively from the cascaded RC filters and from the cascaded cells, and a low-pass filter having an input linked to an output of the multiplier and an output which controls the ohmic values of the first, second, third and fourth variable resistors and of the variable resistors of the slaving circuit.

15. Device according to claim 10, wherein the first, second, third and fourth bipolar transistors are npn transistors having respective collectors linked respectively to said second, third, fourth and fifth terminals and respective emitters linked to said first terminal by way of respective filtering capacitors of substantially smaller capacitances than that of said first and second capacitors.