Two-stage switching regulator having low power modes responsive to load power consumption

• US 5,903,138 A
• Filed: 08/22/1997
• Issued: 05/11/1999
• Est. Priority Date: 03/30/1995
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Chee, Alland, Hwang, Jeffrey H.
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US08/916,570
• Time in Patent Office: 627 Days
• Field of Search: 323/222, 323/224, 323/266, 323/271, 323/282, 323/284, 363/65, 363/890, 363/97, 363/131
• US Class Current: 323/266
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/3353 having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A two-stage switching regulator having low power modes responsive to load power consumption. A first stage of the regulator is a power factor correction (PFC) stage. A second stage is a pulse-width modulating (PWM) stage. When a load draws a high level of current, switching in both stages is enabled. Under certain conditions, switching in either one or both of the stages is disabled by the duty cycle for the corresponding switch falling to zero. When switching in both stages is enabled, as in a normal mode, switching in the PWM stage is then disabled in response to an error signal falling below a first error threshold. When switching in the PFC stage is enabled and switching in the PWM stage is disabled, as in a first low power mode, switching in the PFC stage is then disabled in response to a feedback voltage rising above a first feedback threshold. When switching in both stages is disabled, as in a second low power mode, switching in the PWM stage is then enabled in response to the error voltage rising above a second error threshold, higher than the first error threshold. When switching in the PFC stage is disabled and switching in the PWM stage is enabled, as in a third low power mode, switching in the PFC stage is enabled in response to the feedback voltage falling below the second feedback threshold. As a result of these low power modes, the switching regulator is highly efficient.

Claims

1. A switching regulator comprising:

a. a first stage having a first switch the first stage for receiving an input voltage and for forming an intermediate voltage, wherein the intermediate voltage is regulated according to a duty cycle of the first switch;

b. a second stage having a second switch, the second stage coupled to receive the intermediate voltage for forming an output voltage, wherein the output voltage is regulated according to a duty cycle of the second switch; and

c. a circuit for separately and selectively disabling switching of the first switch and the second switch according to power requirements of a load coupled to receive the output voltage, wherein the circuit for selectively disabling is coupled to the first stage and to the second stage.

2. The switching regulator according to claim 1 wherein the switching regulator operates in an active one of four modes, selected according to power requirements of the load, wherein in a normal mode, switching of both the first switch and the second switch is enabled;

in a first low power mode, switching of the first switch is enabled and the second switch is disabled;

in a second low power mode, both the first switch and the second switch are disabled; and

, in a third low power mode, the first switch is disabled and switching of the second switch is enabled.

3. The switching regulator according to claim 1 wherein the first stage is power factor correction stage.

4. The switching regulator according to claim 1 wherein the second stage is a pulse-width modulating buck converter stage.

5. The switching regulator according to claim 1 wherein upon enabling switching of the first switch, the duty cycle of the first switch is gradually increased according to a soft-start function.

6. The switching regulator according to claim 1 wherein the duty cycle of the first switch is controlled according to a level of a feedback signal, wherein the feedback signal is representative of a level of the intermediate voltage.

7. The switching regulator according to claim 6 wherein the duty cycle of the second switch is controlled according to a level of an error signal, wherein the error signal is representative of a difference between the output voltage and a desired output voltage.

8. The switching regulator according to claim 7 wherein the circuit for selectively disabling switching disables the second switch when the error signal falls below a first error threshold, thereby the switching regulator enters the first low power mode.

9. The switching regulator according to claim 8 wherein when the switching regulator is in the first low power mode, the circuit for selectively disabling enables switching of the second switch when the error signal exceeds the first error threshold, thereby the switching regulator enters the normal mode.

10. The switching regulator according to claim 8 wherein when the switching regulator is in the first low power mode, the circuit for selectively disabling disables the first switch when the feedback signal exceeds a first feedback threshold, thereby the switching regulator enters the second low power mode.

11. The switching regulator according to claim 10 wherein when the switching regulator is in the second low power mode, the circuit for selectively disabling enables switching of the first switch when the feedback signal falls below a second feedback threshold, thereby the switching regulator returns to the first low power mode, and wherein the second feedback threshold is lower than the first feedback threshold.

12. The switching regulator according to claim 10 wherein when the switching regulator is in the second low power mode, the circuit for selectively disabling enables switching of the second switch when the error signal exceeds a second error threshold, thereby the switching regulator enters a third low power mode, and wherein the second error threshold is higher than the first error threshold.

13. The switching regulator according to claim 12 wherein when the switching regulator is in the third low power mode, the circuit for selectively disabling enables the first switch when the feedback signal falls below a second feedback threshold, thereby the switching regulator returns a normal mode wherein switching of the first switch and the second switch is enabled, and wherein the second feedback threshold is lower than the first feedback threshold.

14. The switching regulator according to claim 12 wherein when the switching regulator is in the third low power mode, the circuit for selectively disabling disables the second switch when the error signal falls below the second error threshold, thereby the switching regulator enters the second low power mode.

15. The switching regulator according to claim 6 wherein the circuit for selectively disabling switching comprises:

a. a first comparator having a first input, a second input and an output, wherein the first input of the first comparator is coupled to receive the feedback voltage and the second input of the first comparator is coupled to receive a first feedback threshold voltage;

b. a second comparator having a first input, a second input and an output, wherein the first input of the second comparator is coupled to receive the feedback voltage and wherein the second input of the second comparator is coupled to receive a second feedback threshold voltage;

c. a third comparator having a first input, a second input and an output, wherein the first input of the third comparator is coupled to receive the error signal and the second input is coupled to a receive an error threshold voltage and wherein the output of the third comparator is coupled to selectively disable the second switch; and

d. a flop-flop having a first input for placing the flip-flop in a first condition and a second input for placing the flip-flop in a second condition, wherein the first input is coupled to the output of the second comparator and the second input is coupled to receive a logical combination of the output of the first comparator and the output of the third comparator, wherein the first switch is selectively disabled depending upon whether the flip-flop is in the first condition or in the second condition.

16. The switching regulator according to claim 15 wherein the first feedback threshold is higher than the second feedback threshold.

17. The switching regulator according to claim 15 wherein a level of the error threshold voltage depends upon whether the flip-flop is in the first condition or in the second condition.

18. A method of conserving power consumed by a switching regulator wherein the switching regulator includes a first stage having a first switch and a second stage having a second switch and wherein the first stage supplies an intermediate signal to the stage and wherein second stage forms an output signal for supplying power to a load, the method comprising:

a. operating the switching regulator in a normal mode wherein a duty cycle of the first switch is adjusted according to a level of the intermediate signal and wherein a duty cycle of the second switch is adjusted according to difference between the output signal and a desired output signal;

b. operating the switching regulator in a first low power mode when the difference between the output signal and the desired output signal is lower than a first error threshold wherein the duty cycle of the first switch is adjusted according to a level of the intermediate output signal and the duty cycle of the second switch is zero; and

c. operating the switching regulator in a second low power mode when the intermediate output signal is higher than a first feedback threshold wherein the duty cycle of the first switch is zero and wherein the duty cycle of the second switch is zero.

19. The method according to claim 18 further comprising a step of operating the switching regulator in the first low power mode after operating the switching regulator in the second low power mode upon the intermediate signal becoming lower than a second feedback threshold wherein the second feedback threshold is lower the first feedback threshold.

20. The method according to claim 19 wherein upon leaving the second low power mode, the duty cycle of the first switch is gradually increased according to a soft-start function.

21. The method according to claim 18 further comprising a step of operating the switching regulator in a third low power mode after operating the switching regulator in the second low power mode upon the difference between the output signal and the desired output signal becoming higher than a second error threshold wherein the duty cycle of the first switch is zero and the duty cycle of the second switch is adjusted according to the difference between the output signal and the desired output signal.

22. The method according to claim 21 further comprising a step of operating the switching regulator in the normal mode after operating the switching regulator in the third low power mode upon the intermediate signal becoming lower than the second feedback threshold wherein the second feedback threshold is lower the first feedback threshold.

23. The method according to claim 21 wherein the second error threshold is higher than the first error threshold.

24. The method according to claim 18 wherein the switching regulator operates in the first low power mode only after having been operated in the normal mode.

25. The method according to claim 24 wherein the switching regulator operates in the second low power mode only after having been operated in the first low power mode.