System and method for high-speed skew-insensitive multi-channel data transmission

  • US 5,905,769 A
  • Filed: 05/07/1996
  • Issued: 05/18/1999
  • Est. Priority Date: 05/07/1996
  • Status: Expired due to Term
First Claim
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1. A digital phase-locked loop comprising:

  • a phase aligning window, responsive to a phase alignment value, for receiving as input a plurality of oversampled bits, deriving a plurality of phase-aligned oversampled bits by adjusting a window according to said phase alignment value, and providing said plurality of phase-aligned oversampled bits as output;

    a phase detection circuit for receiving as input said plurality of phase-aligned oversampled bits and producing as output a set of composite phase signals, said phase detection circuit including;

    a plurality of phase-detecting cells, each of said phase-detecting cells receiving as input one of said plurality of phase-aligned oversampled bits determining a phase condition for said one of said plurality of phase-aligned oversampled bits and producing as output one of a plurality of sets of phase signals indicative of said phase condition;

    an up-down decision circuit receiving as input said plurality of sets of phase signals from the plurality of phase-detecting cells, and producing as output a set of composite phase signals;

    a digital filter receiving as input a series of sets of composite phase signals from the up-down decision circuit, and producing as output a set of phase adjustment recommendation signals; and

    a phase-adjusting finite state machine (FSM) receiving as input said set of phase adjustment recommendation signals and producing as output said phase alignment value.

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