Integrated circuit with programmable bus configuration
First Claim
1. An integrated circuit comprising a processor and a given number of terminals which may be configured for communicating with a selected type of external bus,characterized in that said integrated circuit further comprises a bus controller for supplying an initial address to an external memory over said external bus during a bus configuration period, and fetching bus configuration information from said external memory over said external bus, with said fetching utilizing a fewer number of terminals than said given number, and configuring said integrated circuit so that said processor can communicate data over said external bus;
- wherein said controller fetches said bus configuration information during an initial fetch that does not result in an instruction being executed by said processor.
4 Assignments
0 Petitions
Accused Products
Abstract
A technique for configuring a processor allows the processor to interface with external buses of different types; for example, busses having different data widths. Configuration data is stored in a memory, typically a read-only memory, and transferred to the processor during a system configuration period. An initial configuration fetch may be accomplished to retrieve the configuration information prior to executing an actual processor instruction. Alternatively, the configuration information may be included in an actual instruction word. The system configuration period typically occurs during the initial power-on sequence, but may occur at other times.
67 Citations
32 Claims
-
1. An integrated circuit comprising a processor and a given number of terminals which may be configured for communicating with a selected type of external bus,
characterized in that said integrated circuit further comprises a bus controller for supplying an initial address to an external memory over said external bus during a bus configuration period, and fetching bus configuration information from said external memory over said external bus, with said fetching utilizing a fewer number of terminals than said given number, and configuring said integrated circuit so that said processor can communicate data over said external bus; wherein said controller fetches said bus configuration information during an initial fetch that does not result in an instruction being executed by said processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
9. An integrated circuit comprising a processor and a given number of terminals which may be configured for communicating with a selected type of external bus,
characterized in that said integrated circuit further comprises a bus controller for supplying an initial address to an external memory over said external bus during a bus configuration period, and fetching bus configuration information from said external memory over said external bus, with said fetching utilizing a fewer number of terminals than said given number, and configuring said integrated circuit so that said processor can communicate data over said external bus; wherein said controller fetches said bus configuration information during an initial fetch that also fetches an instruction word that is executed by said processor. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
17. A method of configuring an integrated circuit comprising a processor and a given number of terminals which may be configured for communicating with a selected type of external bus,
characterized by supplying an initial address to an external memory over said external bus and fetching bus configuration information from said external memory over said external bus during a bus configuration period, with said fetching utilizing a fewer number of terminals than said given number, and configuring said integrated circuit so that said processor can communicate data over said bus; wherein said fetching fetches said bus configuration information during an initial fetch that does not result in an instruction being executed by said processor. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
-
25. A method of configuring an integrated circuit comprising a processor and a given number of terminals which may be configured for communicating with a selected type of external bus, characterized by supplying an initial address to an external memory over said external bus and fetching bus configuration information from said external memory over said external bus during a bus configuration period, with said fetching utilizing a fewer number of terminals than said given number, and configuring said integrated circuit so that said processor can communicate data over said bus;
wherein said fetching fetches said bus configuration information during an initial fetch that also fetches an instruction word that is executed by said processor. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
Specification
-
- Resources
-
Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
-
Original AssigneeLucent Technologies, Inc. (Nokia Corporation)
-
InventorsLittle, Trevor Edward, Betker, Michael Richard
-
Primary Examiner(s)Sheikh, Ayaz R.
-
Assistant Examiner(s)Etienne, Ario
-
Application NumberUS08/559,868Time in Patent Office1,289 DaysField of Search395/284, 395/828, 395/830, 395/307US Class Current710/104CPC Class CodesG06F 15/177 Initialisation or configura...G06F 9/4411 Configuring for operating w...
