Method of forming a contact hole in an interlevel dielectric layer using dual etch stops

• US 5,912,188 A
• Filed: 08/04/1997
• Issued: 06/15/1999
• Est. Priority Date: 08/04/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Kadosh, Daniel, Hause, Frederick N.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/905,686
• Time in Patent Office: 680 Days
• Field of Search: 438/576, 438/578, 438/586, 438/618, 438/630, 438/637, 438/638, 438/649, 438/675, 438/682, 438/692, 438/733, 438/738, 438/740, 438/743, 438/744
• US Class Current: 438/740
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.

Claims

1. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising:

providing a semiconductor substrate;

forming a gate over the substrate,

forming a source/drain region in the substrate;

providing a source/drain contact electrically coupled to the source/drain region;

forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact;

forming an etch mask over the interlevel dielectric layer;

applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer;

applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and

applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer.

2. The method of claim 1, wherein the gate has a greater thickness than a combined thickness of the second and third dielectric layers.

3. The method of claim 1, wherein the first, second and third etches are anisotropic etches and the contact hole has straight sidewalls.

4. The method of claim 1, wherein the second etch is highly selective of the source/drain contact with respect to the third dielectric layer.

5. The method of claim 1, wherein the source/drain contact is the source/drain region.

6. The method of claim 1, wherein the source/drain contact is a silicide contact on the source/drain region.

7. The method of claim 1, wherein the first and third dielectric layers are selected from the group consisting of silicon dioxide and silicon oxyfluoride, and the second dielectric layer is selected from the group consisting of silicon nitride, silicon oxynitride, hydrogen silsesquioxane, fluorinated polyimide, poly-phenylquinoxaline, polyquinoline, and methysilsesquixane polymer.

8. The method of claim 1, wherein the gate is polysilicon and the etch mask is photoresist.

9. The method of claim 1, including manufacturing an integrated circuit chip that includes the interlevel dielectric layer.

10. The method of claim 1, including manufacturing an electronic system that includes a microprocessor, a memory and a system bus, and that further includes the interlevel dielectric layer.

11. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising:

providing a semiconductor substrate;

forming a gate insulator over the substrate;

forming a gate on the gate insulator;

forming a source/drain region in the substrate;

providing a source/drain contact electrically coupled to the source/drain region;

forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, including forming the first dielectric layer on the second dielectric layer and forming the second dielectric layer on the third dielectric layer, wherein the gate has a greater thickness than a combined thickness of the second and third dielectric layers;

forming an etch mask over the interlevel dielectric layer;

applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer;

applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and

applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer.

12. The method of claim 11, wherein the second anisotropic etch is highly selective of the source/drain contact with respect to the third dielectric layer.

13. The method of claim 11, wherein the source/drain contact is the source/drain region.

14. The method of claim 11, wherein the source/drain contact is a silicide contact on the source/drain region.

15. The method of claim 11, wherein the interlevel dielectric layer consists of the first, second and third dielectric layers.

16. The method of claim 11, wherein the first and third dielectric layers are the same material.

17. The method of claim 16, wherein the first and third dielectric layers are selected from the group consisting of silicon dioxide and silicon oxyfluoride, and the second dielectric layer is selected from the group consisting of silicon nitride, silicon oxynitride, hydrogen silsesquioxane, fluorinated polyimide, poly-phenylquinoxaline, polyquinoline, and methysilsesquixane polymer.

18. The method of claim 11, wherein the gate is polysilicon and the etch mask is photoresist.

19. The method of claim 11, including forming a conductive plug in the contact hole that contacts the source/drain contact.

20. The method of claim 19, including forming a metal-1 pattern on the first dielectric layer that contacts the conductive plug.

21. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising the sequence set forth:

providing a semiconductor substrate;

forming a gate oxide over the substrate;

forming a polysilicon gate on the gate oxide;

forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region, wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate;

forming an interlevel dielectric layer that consists of first, second and third dielectric layers over the source/drain contact, including forming the first dielectric layer on the second dielectric layer, forming the second dielectric layer on the third dielectric layer, and forming the third dielectric layer on the source/drain contact, wherein the first and third dielectric layers are the same material, the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers, and the first dielectric layer has a greater thickness than the polysilicon gate;

forming a photoresist layer on the interlevel dielectric layer;

applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer;

applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and

applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask, thereby forming a third hole through the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer.

22. The method of claim 21, wherein the second anisotropic etch is highly selective of the source/drain contact with respect to the third dielectric layer.

23. The method of claim 21, wherein the source/drain contact is the source/drain region.

24. The method of claim 21, wherein the source/drain contact is a silicide contact on the source/drain region.

25. The method of claim 21, wherein the first and third dielectric layers are the same material.

26. The method of claim 25, wherein the first and third dielectric layers are selected from the group consisting of silicon dioxide and silicon oxyfluoride.

27. The method of claim 26, wherein the second dielectric layer is selected from the group consisting of silicon nitride, silicon oxynitride, hydrogen silsesquioxane, fluorinated polyimide, polyphenylquinoxaline, polyquinoline, and methysilsesquixane polymer.

28. The method of claim 21, including planarizing the interlevel dielectric by applying chemical-mechanical polishing before forming the photoresist layer.

29. The method of claim 21, including the following steps in the sequence set forth:

stripping the photoresist layer after forming the contact hole;

forming a conductive plug in the contact hole that contacts the source/drain contact; and

forming a metal-1 pattern on the first dielectric layer that contacts the conductive plug.

30. The method of claim 29, wherein:

the contact hole exposes the source/drain contact, a dielectric isolation region in the substrate, and a second source/drain contact electrically coupled to a second source/drain region in the substrate; and

the conductive plug provides a local interconnect between the source/drain contact and the second source/drain contact.