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Charge pump circuit for voltage boosting in integrated semiconductor circuits

  • US 5,912,560 A
  • Filed: 02/25/1997
  • Issued: 06/15/1999
  • Est. Priority Date: 02/25/1997
  • Status: Expired due to Term
First Claim
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1. A charge pump comprising:

  • an initial charge transfer stage having a supply terminal, an initial output terminal and an initial clock terminal;

    a load capacitor;

    a boost section having a boost input terminal connected to said initial output terminal and a boost output terminal connected to said load capacitor; and

    first and second oppositely clocked lines;

    wherein said initial charge transfer stage additionally comprises;

    an initial charge transfer switch, having an initial transfer switch control gate, which conditionally connects said supply terminal to said initial output terminal; and

    an initial gate controller connected to said initial clock terminal and having a transfer state and a non-transfer state wherein, in said transfer state, said initial gate controller applies voltage to said initial transfer switch control gate to transfer charge from the supply terminal to the initial output terminal and in said non-transfer state, disables any charge transfer;

    wherein said boost section comprises at least two boost stages and wherein each boost stage comprises;

    a boost input terminal, a boost output terminal, a boost clock terminal and a boost capacitor terminal;

    a boost capacitor connected between said boost input terminal and said boost capacitor terminal;

    a boost charge transfer switch, having a boost transfer switch control gate, which conditionally connects said boost input terminal to said boost output terminal;

    a boost gate controller connected to said boost clock terminal and having a transfer state and a non-transfer state wherein, in said transfer state, said boost gate controller applies voltage to said boost transfer switch control gate to transfer charge from said boost input terminal to the boost output terminal and in said non-transfer state, disables any charge transfer;

    wherein said first control line is connected to said initial clock terminal, to the boost capacitor terminals of odd numbered boost stages and to the boost clock terminals of even numbered boost stages; and

    wherein said second control line is connected to the boost capacitor terminals of even numbered boost stages and to the boost clock terminals of odd numbered boost stages.

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