Repair fuse circuit performing complete latch operation using flash memory cell

• US 5,912,841 A
• Filed: 12/23/1997
• Issued: 06/15/1999
• Est. Priority Date: 12/24/1996
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Seong Durk
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/997,063
• Time in Patent Office: 539 Days
• Field of Search: 365/185.09, 365/154, 365/189.05, 365/225.7, 365/185.33
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

The present invention provides a repair fuse circuit capable of performing stable latch operation. The present invention improves the reliability of the repair fuse circuit using flash memory cells, by performing the initialization of the cross-coupled latch circuit at a high voltage level. The repair fuse circuit of a cross-coupled latch structure includes a voltage increasing element for temporally increasing voltage level of the cross-coupled latch circuit and a controller for controlling the voltage increasing element. As a result, the repair fuse circuit is initialized in a high logic state.

Claims

1. A repair fuse circuit of a cross-coupled latch circuit, comprising:

a first flash memory cell coupled to a first current providing means at a first node;

at least two second flash memory cells coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;

a first means for precharging the first and second nodes; and

a second means for generating a control signal to control the first means in order that the first means temporally precharges the first and second nodes,

whereby the repair fuse circuit is initialized in a high logic state.

2. The repair fuse circuit in accordance with claim 1, wherein the first means for precharging the first and second nodes comprises a first pull-up transistor coupled to the first node and a second pull-up transistor coupled to the second node.

3. The repair fuse circuit in accordance with claim 1, wherein the second means for generating a control signal comprises:

a voltage detecting means for detecting whether the power supply increases up to a selected voltage level; and

a pulse generating means for receiving an output from the voltage detecting means and generating the control signal.

4. The repair fuse circuit in accordance with claim 3, wherein the pulse generating means comprises:

a plurality of first inverting means coupled in series to the voltage detecting means;

at least one capacitive coupling means coupled in parallel to the first inverting means;

an NAND logic means for NANDing outputs from two inverting means of a plurality of the first inverting mean; and

a plurality of second inverting means coupled in series the NAND logic means.

5. The repair fuse circuit in accordance with claim 4, wherein the capacitive coupling means is an n-channel MOS transistor having a gate connected to the output terminal of the first inverting means and source and drain connected to a ground voltage level.

6. A repair fuse circuit of a cross-coupled latch circuit, comprising:

a first flash memory cell coupled to a first current providing means at a first node;

at least two second flash memory cells which are coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;

enable delay means for increasing a voltage level in the first and second nodes, by cutting off a current path of the cross-coupled latch circuit.

7. The repair fuse circuit in accordance with claim 6, wherein the enable delay means comprises:

a voltage detecting means for detecting whether the power supply increases up to a selected voltage level;

an inverting means for inverting an output from the voltage detecting means for providing an enable signal for the cross-coupled latch circuit.

8. A repair fuse circuit of a cross-coupled latch circuit in a flash memory device, comprising:

a flash memory cell coupled to a first current providing means at a first node;

at least two flash memory cells which are coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;

a voltage increasing means for temporally increasing voltage level at the first and second nodes; and

a control means for controlling the voltage increasing means,

whereby the repair fuse circuit is initialized in a high logic state.

9. The repair fuse circuit in accordance with claim 8, wherein the voltage increasing means comprises a first pull-up transistor coupled to the first node and a second pull-up transistor coupled to the second node.

10. The repair fuse circuit in accordance with claim 8, wherein the control means comprises:

a voltage detecting means for detecting whether the power supply increases up to a selected voltage level; and

an enable delay means for increasing a voltage level in the first and second nodes, by cutting off a current path of the cross-coupled latch circuit.

11. The repair fuse circuit in accordance with claim 8, wherein the control means comprises:

a voltage detecting means for detecting whether an applied power supply increases up to a selected voltage level; and

a pulse generating means for receiving an output from the voltage detecting means and generating the control signal.

12. The repair fuse circuit in accordance with claim 11, wherein the pulse generating means comprises:

a plurality of first inverting means coupled in series to the voltage detecting means;

at least one capacitive coupling means coupled in parallel to the first inverting means;

an NAND logic means for NANDing outputs from two inverting means of a plurality of the first inverting mean; and

a plurality of second inverting means coupled in series the NAND logic means.

13. The repair fuse circuit in accordance with claim 12, wherein the capacitive coupling means is an n-channel MOS transistor having a gate connected to the output terminal of the first inverting means and source and drain connected to a ground voltage level.