Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing

  • US 5,913,712 A
  • Filed: 03/12/1997
  • Issued: 06/22/1999
  • Est. Priority Date: 08/09/1995
  • Status: Expired due to Term
First Claim
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1. A process for planarizing a layer on a substrate, comprising the steps of:

  • a first polishing step comprising polishing said layer on a first polishing pad;

    a second polishing step comprising polishing said layer on a second polishing pad having a higher compressibility than said first polishing pad at an effective pressure to reduce scratches in said layer; and

    a third rising step comprising rinsing said layer on said second polishing pad using water.

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