Advanced modular cell placement system with coarse overflow remover
First Claim
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1. A computer implemented method for optimizing cell placement for integrated circuit design, comprising the steps of:
- a. segmenting an integrated circuit surface abstraction into a plurality of regions;
b. assigning a plurality of cells to one of the regions;
c. creating a list of said plurality of cells in order of decreasing cell height;
d. reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region and thereafter assigning the remaining cells outside of the region.
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Abstract
A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.
94 Citations
10 Claims
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1. A computer implemented method for optimizing cell placement for integrated circuit design, comprising the steps of:
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a. segmenting an integrated circuit surface abstraction into a plurality of regions; b. assigning a plurality of cells to one of the regions; c. creating a list of said plurality of cells in order of decreasing cell height; d. reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region and thereafter assigning the remaining cells outside of the region. - View Dependent Claims (2, 3)
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4. A computer implemented method for optimizing cell placement for integrated circuit design, comprising the steps of:
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a. segmenting an integrated circuit surface abstraction into a plurality of regions; b. assigning a plurality of cells to one of the regions; c. reassigning said cells such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region and thereafter assigning the remaining cells outside of the region, wherein the remaining cells are assigned to the regions closest to the original region using Manhattan distance. - View Dependent Claims (5, 6, 7)
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8. A computer storage device containing instructions for a computer to optimize cell placement in an integrated circuit including the following computer implemented steps:
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a. segmenting an integrated circuit surface abstraction into a plurality of regions; b. assigning a plurality of cells to one of the regions; and c. reassigning said cells such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region and thereafter assigning the remaining cells outside of the region, wherein instruction (c) reassigns the remaining cells to the regions closest to the original region using Manhattan distance. - View Dependent Claims (9, 10)
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Specification
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Current AssigneeBell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsScepanovic, Ranko, Andreev, Alexander E., Koford, James S.
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Primary Examiner(s)Teska, Kevin J.
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Assistant Examiner(s)Kik, Phallaka
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Application NumberUS08/672,334Time in Patent Office1,089 DaysField of Search364/488-491, 364/578US Class Current716/122CPC Class CodesG06F 30/392 Floor-planning or layout, e...
