Method and system for generating a mask layout of an optical integrated circuit

• US 5,914,889 A
• Filed: 09/13/1996
• Issued: 06/22/1999
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Cohen, Leonard George, Henry, Charles Howard, Li, Yuan P., Schwartz, Morton I., Wang, Yan, Yaffe, Henry Howard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/713,582
• Time in Patent Office: 1,012 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500, 385/14, 385/50, 385/129
• US Class Current: 716/52
• CPC Class Codes: G02B 2006/12173 Masking
• CPC Class Codes: G02B 6/12 of the integrated circuit kind electric integrated circuits H01L27/00
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A computer system and method provide a CAD tool by which a mask for an application specific optical integrated circuit, chip, or wafer may be generated both easily and quickly. The method involves the step of receiving the design for an optical circuit with the circuit design including at least one optical component. Each optical component in the optical circuit is defined by one or more geometric shapes, such as a trapezoid, rectangle, or an arcuate polygon. The method further includes the step of retrieving parameters which define the manufacturing standard by which the optical circuit will be fabricated as well as parameters which define the optical components in the optical circuit. Based on the parameters and the geometric shapes, a plot is generated which forms a mask layout for the optical circuit. The mask layout can then be viewed by a graphical editor whereby a designer can receive visual confirmation that the mask layout accurately portrays the desired optical circuit, chip, or wafer.

Claims

1. A computer-implemented method for generating a mask layout of an optical integrated circuit, comprising the steps of:

providing a plurality of selections;

representing a plurality of optical components with said selections, said plurality of optical components associated with a plurality of geometric shapes;

forming a design for the optical integrated circuit with said optical circuit including at least one of said optical components;

receiving an input;

selecting at least one of said selections during said forming step in response to said input;

associating said one of said selections with said one of said optical components;

defining said one optical component with at least one geometric shape;

retrieving parameters defining a manufacturing standard and defining dimensions of the geometric shape associated with said one optical component; and

generating a plot of the geometric shape for each optical component associated with the selections that are selected in said selecting step;

wherein said plot of the geometric shape for each optical component in the optical circuit is the mask layout used to fabricate the optical integrated circuit on a substrate, said mask layout defining at least one optical waveguide in said substrate.

2. The computer-implemented method as set forth in claim 1, wherein said step of forming said design for the optical circuit comprises the step of designing said optical circuit.

3. The method as set forth in claim 1, wherein said step of defining each optical component in said optical circuit with at least one geometric shape comprises the step of dividing the optical component into a plurality of geometric shapes.

4. The method as set forth in claim 1, wherein said step of retrieving parameters for defining the manufacturing standard comprises the step of selecting any one of a plurality of different manufacturing standards.

5. The method as set forth in claim 1, wherein said step of generating the plot based on the at least one geometric shape for each optical component in the optical circuit comprises the step of transferring the geometric shape for each optical component onto a grid.

6. The method as set forth in claim 1, wherein said step of generating said plot comprises the step of generating said plot for an optical chip.

7. The method as set forth in claim 1, wherein said step of generating said plot comprises the step of generating said plot for a wafer.

8. The method as set forth in claim 1, further comprising the steps of receiving a second optical design for a second optical circuit, defining each optical component in said second optical circuit with at least one geometric shape, retrieving parameters for defining said manufacturing standard and for defining said dimensions of each geometric shape for the second optical circuit, and generating said plot to include each geometric shape for each optical component in the second optical circuit.

9. The method as set forth in claim 1, further comprising the step of adding chip labels and markers to said plot.

10. The method as set forth in claim 1, further comprising the step of displaying each geometric shape defining said plot.

26. The method of claim 1, further comprising the steps of:

generating a spectral analysis for said optical integrated circuit based on said selections that are selected in said selecting step;

displaying said spectral analysis; and

changing, subsequent to said displaying step, selected ones of said selections.

11. A computer-readable medium encoded with a computer program for use in generating a mask layout of an optical integrated circuit, said computer program used with a computer system to perform the steps of:

providing a plurality of icons representing optical components, said optical components associated with geometric shapes;

receiving an input;

selectively combining said icons in response to said input;

forming a design, based on said receiving step, for the optical circuit with said optical circuit including at least one of said optical components;

defining said one optical component with at least one geometric shape;

retrieving parameters defining a manufacturing standard and defining dimensions of the geometric shape associated with said one optical component; and

translating the icons combined in said combining step into a plot that indicates the geometric shape for each optical component in the optical circuit.

12. The computer readable medium as set forth in claim 11, wherein said computer readable medium is a magnetic storage medium.

13. The computer readable medium as set forth in claim 11, wherein said computer readable medium is an optical storage medium.

14. The computer readable medium as set forth in claim 11, wherein said computer readable medium comprises semiconductor memory.

27. The medium of claim 11, wherein said computer program is further used with said computer system to perform the steps of:

receiving a second optical design for a second optical circuit;

defining each optical component in said second optical circuit with at least one geometric shape;

retrieving parameters for defining said manufacturing standard and for defining said dimensions of each geometric shape for the second optical circuit; and

generating said plot to include each geometric shape for each optical component in the second optical circuit.

15. A system for generating a mask layout of an optical integrated circuit, comprising:

a central processing unit;

a memory accessible by the central processing unit;

means for displaying a plurality of selections, said selections corresponding with a plurality of optical components, said plurality of optical components associated with a plurality of geometric shapes;

means for selecting one of said selections;

means for designing the optical integrated circuit based on selected ones of said selections, said optical circuit including at least one of said optical components;

means for defining said one optical component with at least one geometric shape;

means for retrieving parameters defining a manufacturing standard and defining dimensions of the geometric shape associated with said one optical component; and

means for generating a plot of the geometric shape for each optical component that corresponds with said selected ones of said selections;

wherein said plot of the geometric shape for said each optical component is the mask layout used to fabricate the optical integrated circuit on a substrate, said mask layout defining at least one optical waveguide in said substrate.

16. The system as set forth in claim 15, further comprising means for displaying said mask layout to illustrate said geometric shapes plotted and thereby to illustrate said waveguide.

17. The system as set forth in claim 16, further comprising means for expanding a view of said plot across a width of said waveguide relative to a view of said plot along a length of said waveguide.

18. The system as set forth in claim 15, further comprising means for selecting said manufacturing standard from a plurality of manufacturing standards stored in said memory.

19. The system as set forth in claim 15, further comprising means for storing said mask layout in said memory.

20. The system as set forth in claim 15, wherein said generating means generates the plot for a chip.

21. The system as set forth in claim 15, wherein said generating means generates the plot for a wafer.

22. The system as set forth in claim 21, wherein said generating means adds chip labels and markers to said plot.

23. The system as set forth in claim 15, wherein said optical component comprises an optical device and said generating means generates the plot of said optical device.

24. The system as set forth in claim 15, wherein said optical component comprises an optical interconnect and said generating means generates the plot of said optical interconnect.

25. The system as set forth in claim 15, wherein said optical component comprises an optical end port and said generating means generates the plot of said optical end port.