Integrated circuit I/O using a high performance bus interface

• US 5,915,105 A
• Filed: 11/26/1997
• Issued: 06/22/1999
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/979,127
• Time in Patent Office: 573 Days
• Field of Search: 395/556, 395/309, 365/233, 365/230.03, 365/233.5, 711/100, 711/111
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A memory device comprising:

a first circuit for receiving a bus clock from a bus and for generating at least one internal clock; and

receiver circuitry coupled to the first circuit to receive the at least one internal clock, the receiver circuit samples information on the bus in response to the at least one internal clock to acquire even bus cycle information and odd bus cycle information from the bus.

2. A memory device comprising:

a first circuit for receiving an external clock from a bus and for providing a first internal clock and a second internal clock; and

receiver circuitry coupled to the first circuit to receive the first internal clock and the second internal clock, the receiver circuitry samples information on the bus in response to the first internal clock and the second internal clock, wherein the receiver circuitry comprises;

a first input receiver coupled to the first circuit, the first input receiver samples information on the bus in response to the first internal clock to acquire even bus cycle information; and

a second input receiver coupled to the first circuit, the second input receiver samples information on the bus in response to the second internal clock to acquire odd bus cycle information.

3. A semiconductor device having memory, the device comprising:

a clock circuit to provide a first clock signal and a second clock signal;

a first input receiver coupled to the clock circuit to receive the first clock signal, wherein in response to the first clock signal, the first input receiver senses a bus signal on a bus;

a second input receiver coupled to the clock circuit to receive the second clock signal, wherein in response to the second clock signal, the second input receiver senses the bus signal, and wherein the first and second input receivers are selected alternately by the clock circuit.

4. The semiconductor device of claim 3 wherein the second clock signal is a complement of the first clock signal.

5. The semiconductor device of claim 4 wherein the clock circuit provides the first and second clock signals in response to a clock signal which is generated externally to the semiconductor device.

6. The semiconductor device of claim 3 further including clock receiver circuitry to receive a first external clock signal and wherein the clock circuit includes a delay locked loop, coupled to the clock receiver circuitry, to generate the first clock signal using at least the first external clock signal.

7. The semiconductor device of claim 3 further including clock receiver circuitry to receive first and second external clock signals and wherein the clock circuit includes a delay locked loop, coupled to the clock receiver circuitry, to generate the first clock signal using the first and second external clock signals.

8. The semiconductor device of claim 3 further including clock receiver circuitry to receive first and second external clock signals and wherein the clock circuit is coupled to the clock receiver circuitry and generates the first clock signal using the first external clock signal and the second external clock signal.

9. The memory device of claim 8 wherein the first external clock signal and a second external clock signal are substantially complementary.

10. A memory device comprising:

a first circuit to receive an external clock signal and to provide a first internal clock signal and a second internal clock signal;

a multiplexer coupled to the first circuit to receive the first internal clock and second internal clock, the multiplexer including an output and first and second inputs;

a first output line coupled to the first input of the multiplexer;

a second output line coupled to the second input of the multiplexer;

an output driver having an output coupled to the bus, an input coupled to the output of the multiplexer, the output driver for driving data on the bus in response to the output of the multiplexer; and

wherein the multiplexer couples the first output line to the output of the multiplexer in response to the first internal clock to provide even bus cycle information to the bus, and couples the second output line to the output of the multiplexer in response to the second internal clock to provide odd bus cycle information to the bus.

11. A memory device comprising:

a first circuit to generate at least one internal clock; and

output circuitry having a pair of inputs and an output, the output being coupled to a bus, the output circuitry alternately selects one or the other of the pair of inputs in response to the at least one internal clock to provide even and odd bus cycle information to the bus.

12. A semiconductor device having memory, comprising:

A clock circuit to provide a first clock signal and a second clock signal;

a multiplexer coupled to the clock circuit to receive the first and second clock signals, the multiplexer having an output, a first input coupled to a first output line and a second input coupled to a second output line;

an output driver including;

(1) an output coupled to a bus and

(2) an input coupled to an output of the multiplexer, wherein the output driver drives data onto the bus;

wherein the multiplexer couples the first output line to the output of the multiplexer in response to the first clock signal;

and the multiplexer couples the second output line to the output of the multiplexer in response to the second clock signal.

13. The semiconductor device of claim 12 further including clock receiver circuitry to receive a first external clock signal and wherein the clock circuit includes a delay locked loop, coupled to the clock receiver circuitry, to generate the first clock signal using at least the first external clock signal.

14. The semiconductor device of claim 12 further including clock receiver circuitry to receive first and second external clock signals and wherein the clock circuit includes a delay locked loop, coupled to the clock receiver circuitry, to generate the first clock signal using the first external clock signal and the second external clock signal.

15. The semiconductor device of claim 12 further including clock receiver circuitry to receive at least a first external clock signal and wherein the clock circuit is coupled to the clock receiver circuitry and generates the first and second clock signals using at least the first external clock signal.

16. The semiconductor device of claim 15 wherein the first external clock signal and a second external clock signal are substantially complementary.

17. A synchronous random access memory, comprising:

a selection circuit for generating a first selection signal and a second selection signal in response to at least one bus clock;

a first input receiver coupled to the first selection circuit, the first input receiver, in response to the first selection signal, senses a signal on a bus;

a second input receiver coupled to the second selection circuit, the second input receiver, in response to the second selection signal, senses a signal on the bus, wherein selection circuit selects the first and second input receivers to sense signals on the bus synchronous with respect to the at least one bus clock.

18. The synchronous memory of claim 17 wherein the first selection signal is a first clock signal and the second selection signal is a second clock signal wherein the first and second clock signals are complementary.

19. The synchronous memory of claim 17 wherein the first selection signal is a first clock signal and the second selection signal is a second clock signal and wherein the selection circuit generates the first and second clock signals in response to at least two bus clocks which are generated externally to the memory.

20. A synchronous random access memory, comprising:

a selection circuit for providing a first selection signal and a second selection signal in response to at least one bus clock;

a multiplexer coupled to the selection circuit, the multiplexer includes an output and at least first and second inputs;

an output driver including;

(1) an output coupled to a bus and,

(2) an input coupled to the output of the multiplexer, wherein the output driver drives data onto the bus;

a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to the first selection signal;

a second output line coupled the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to the second selection signal;

wherein the output driver drives data onto the bus synchronously with respect to at least the one bus clock.

21. The synchronous memory of claim 20, wherein the first selection signal is a first clock signal and the second selection signal is a second clock signal that is a complement of the first clock signal and wherein the selection circuit generates the first and second clock signals in response to at least two bus clock signals which are generated externally to the memory.

22. The synchronous memory of claim 21, wherein the output driver is a transistor including a first electrode coupled to the bus, a second electrode coupled to a first potential, and a gate coupled to the output of the multiplexer, the transistor being switched on and off in response to the output of the multiplexer.

23. The semiconductor device of claim 20 further including clock receiver circuitry to receive first and second bus clocks and wherein the selection circuit includes delay locked loop circuitry to generate the first and second selection signals using the first and second external clock signals.

24. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

clock receiver circuitry to receive at least one external clock signal;

clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal and a second internal clock signal;

input receiver circuitry coupled to the clock generation circuitry to receive the first and second internal clock signals, the input receiver circuitry samples information on a bus in response to the first and second internal clock signals and synchronously with respect to at least the one external clock signal.

25. The memory device of claim 24 wherein the input receiver circuitry includes:

a first input receiver to sample the information on the bus in response to the first internal clock signal, and

a second input receiver to sample the information on the bus in response to the second internal clock signal.

26. The memory device of claim 25 wherein the first input receiver latches information on the bus in response to a rising edge of the first internal clock signal and the second input receiver latches information on the bus in response to a rising edge of the second internal clock signal.

27. A memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

a first clock receiver to receive a first external clock signal;

a second clock receiver to receive a second external clock signal; and

input receiver circuitry, coupled to the first and second clock receivers, to sample information on a bus synchronously with respect to the first and second external clock signals.

28. The memory device of claim 27 wherein the input receiver circuitry includes a first input receiver to sample the information on the bus synchronously with respect to the first external clock signal and a second input receiver to sample the information on the bus synchronously with respect to the second external clock signal.

29. The memory device of claim 27 wherein the memory device further includes:

first internal clock generation circuitry, coupled to the first clock receiver, to generate a first internal clock signal, and

second internal clock generation circuitry, coupled to the second clock receiver, to generate a second internal clock signal; and

wherein the input receiver circuitry includes a first input receiver to sample the information on the bus synchronously with respect to the first internal clock signal and a second input receiver to sample the information on the bus synchronously with respect to the second internal clock signal.

30. The memory device of claim 29 wherein the first internal clock signal and a second internal clock signal are substantially complementary.

31. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

internal clock generation circuitry to generate a first internal clock signal and a second internal clock signal, wherein the internal clock generation circuit generates the first and second internal clock signals using at least a first external clock;

an output driver, coupled to the internal clock generation circuitry, the output driver outputs data on a bus in response to the first and second internal clock signals and synchronously with respect to at least the first external clock signal.

32. The memory device of claim 31 further including a multiplexer having at least two inputs, the multiplexer being coupled to the first and second internal clock generation circuitry to receive the first and second internal clock signals wherein the first input of the multiplexer is coupled the output driver in response to the first internal clock signal and the second input of the multiplexer is coupled to the gate of the output driver in response to the second internal clock signal.

33. The memory device of claim 31 wherein the output driver outputs data on the bus in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

34. The memory device of claim 31 further including clock receiver circuitry to receive the first external clock and wherein the internal clock generation circuitry includes delay locked loop circuitry, coupled to the clock receiver circuitry, to generate the first internal clock signal and the second internal clock signal using at least the first external clock.

35. The memory device of claim 34 wherein the output driver includes a transistor including a first electrode coupled to the bus, a second electrode coupled to a first potential, and a gate coupled to a multiplexer, wherein the multiplexer includes at least two inputs, the multiplexer being coupled to the first and second internal clock generation circuitry to receive the first and second internal clock signals wherein the first input of the multiplexer is coupled to the gate of the output driver in response to the first internal clock signal and the second input of the multiplexer is coupled to the gate of the output driver in response to the second internal clock signal.

36. A synchronous memory device having at least one memory section which includes a plurality of memory cells, wherein the memory device receives first and second external clock signals and outputs data on a bus, the memory device comprises:

a plurality of output drivers, each output driver being coupled to the bus to output data on the bus synchronously with respect to the first and second external clock signals.

37. The memory device of claim 36 further including internal clock generation circuitry which generates first and second internal clock signals using the first and second external clock signals, and wherein the plurality of output drivers output data on the bus in response to the first internal clock signal and the second internal clock signal.

38. The memory device of claim 37 wherein the first internal clock signal and the second internal clock signal are substantially complementary.

39. The memory device of claim 38 wherein the plurality of output drivers output data on the bus in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

40. The memory device of claim 36 further including clock receiver circuitry to receive the first and second external clock signals, and wherein the memory device further includes delay locked loop circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals.

41. The memory device of claim 40 wherein the plurality of output drivers include a first output driver to output data on the bus in response to the first internal clock signal and a second output driver to output data on the bus in response to the second internal clock signal.

42. The memory device of claim 41 further including:

a first multiplexer coupled to the first output driver;

a second multiplexer coupled to the second output driver; and

wherein the first and second multiplexers provide a first data signal path to the output driver in response to the first internal clock signal and a second data signal path to the output driver in response to the second internal clock signal.

43. A synchronous dynamic random access memory having at least one memory section which includes a plurality of memory cells, the memory device comprises:

internal clock generation circuitry to generate a first internal clock signal and a second internal clock signal;

a multiplexer having an output and at least two inputs, the multiplexer being coupled to internal clock generation circuitry to receive the first and a second internal clocks;

an output driver having an output and an input, the input being coupled to the output of the multiplexer,

a first data output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first data output line to the output of the multiplexer in response to the first internal clock signal; and

a second data output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second data output line to the output of the multiplexer in response to the second internal clock signal

wherein the output driver drives data on a bus synchronously with respect to first and second external clock signals.

44. The memory device of claim 43 further including:

clock receiver circuitry to receive the first internal clock signal and the second internal clock signal;

first delay locked loop, coupled to the clock receiver circuitry, to generate a first internal clock signal, and

second delay locked loop, coupled to the clock receiver circuitry, to generate a second internal clock signal.

45. The memory device of claim 44 wherein the first delay locked loop generates the first internal clock signal using the first and second external clock signals, and the second delay locked loop generates the second internal clock signal using the first and second external clock signal.