Integrated circuit I/O using a high performance bus interface

  • US 5,915,105 A
  • Filed: 11/26/1997
  • Issued: 06/22/1999
  • Est. Priority Date: 04/18/1990
  • Status: Expired due to Fees
First Claim
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1. A memory device comprising:

  • a first circuit for receiving a bus clock from a bus and for generating at least one internal clock; and

    receiver circuitry coupled to the first circuit to receive the at least one internal clock, the receiver circuit samples information on the bus in response to the at least one internal clock to acquire even bus cycle information and odd bus cycle information from the bus.

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