Apparatus and method for a read-modify-write operation in a dynamic random access memory

• US 5,917,839 A
• Filed: 05/27/1997
• Issued: 06/29/1999
• Est. Priority Date: 06/07/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hashimoto, Masashi, Ghosh, Anjana
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/863,851
• Time in Patent Office: 763 Days
• Field of Search: 371/51.1, 371/48, 371/21.1
• US Class Current: 714/805
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: H03M 13/098 using single parity bit

Abstract

In a dynamic random access memory unit 10, a circuit, 61₀ -61_N.sbsb.--₁, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Claims

1. A synchronous dynamic random access memory unit having read and write operations initiated by an address signal group, a system clock signal and an activation signal;

said memory unit comprising;

a storage cell array for storing data signals; and

control apparatus responsive to address signals, a system clock signal, and a read control signal for retrieving data signals from said storage cell array, said control apparatus including a gate circuit responsive to a non-change in said address signals and a system clock signal for preventing said read control signal from initiating a read operation during a modify portion of a read-modify-write operation.

2. The memory unit of claim 1 wherein said memory operates in a page mode of operation.

3. The memory unit of claim 1 further including:

a parity generation and checking unit; and

a parity bit storage unit for storing a parity bit with each stored data group.

4. The memory unit of claim 1 wherein said gate circuit has:

a plurality of detection circuits, each detection circuit having an address signal applied thereto, an output signal of a detection circuit changing from a first logic state to a second logic state when an applied address signal changes state;

a combining circuit having output signals from said detection circuits applied thereto, an output signal of said combining circuit changing from a third logic state to a fourth logic state when one of said detection circuit output signals changes from said first logic state to said second logic state; and

a gate unit having said combining circuit output signal and a read activation signal applied thereto, said gate unit transmitting said read activation signal when said combining circuit output signal has said fourth logic state.

5. The memory unit of claim 4 wherein an output signal of said gate unit becomes said third logic state in response to timing control signal.

6. A method for executing a read-modify-write operation in a synchronous dynamic random access memory unit, said method comprising the steps of:

during a first system clock period, retrieving a first data group from said memory unit and transmitting said first data group to a central processing unit,

during a second consecutive system clock period, modifying said data group in said central processing unit;

during said second consecutive system clock period, preventing said memory unit from performing a read operation; and

during a third consecutive system clock period, storing said first data group in said memory unit.

7. The method of claim 6 wherein said preventing step includes the step of blocking a memory unit activation and thereby preventing a read or write operation during said modifying step.

8. The method of claim 6 further comprising the step of operating said memory unit in a page mode.

9. The method of claim 6 wherein said retrieving step includes the steps of:

retrieving a parity bit from said storage cell array associated with said retrieved data group;

generating a parity bit from said retrieved data group; and

comparing said retrieved parity bit with said stored parity bit.

10. The method of claim 9 wherein said storing step includes the steps of:

generating a parity bit from said group of data bits to be stored in said memory unit; and

storing said parity bit in a storage cell associated with the storage cells into which said data signals are to be stored.

11. A data processing system comprising:

central processing unit; and

synchronous DRAM memory unit coupled to said central processing unit and exchanging data signals therewith, said central processing unit applying control and address signals to said memory unit, said memory unit including;

a storage cell array into which data signals to be transmitted to the central processor are read and into which data signals from the central processing unit are to be stored; and

a control unit responsive to address and control signals and a system clock signal for activating selected storage cells and initiating read and write operations for said storage cell array, said control unit including a gate circuit responsive to said address signals, a storage cell read signal, and a system clock signal for preventing a read operation during a system clock cycle in which address signals from the next system clock cycle and said system clock cycle are identical.

12. The data processing system of claim 11 wherein said memory unit operating in a page mode.

13. The data processing system of claim 11 wherein said memory unit includes a parity generating and checking circuit.

14. The data processing system of claim 11 wherein said gate circuit has:

a gate unit for transmitting said read activation in response to a change signal; and

a plurality of change circuits, each change circuit having an address signal applied thereto, wherein a change circuit generates a change signal when an applied address signal changes states.