General-purpose customizable memory controller

• US 5,918,242 A
• Filed: 02/24/1997
• Issued: 06/29/1999
• Est. Priority Date: 03/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yanes, Adalberto Guillermo, Sarma, Sudha
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US08/805,095
• Time in Patent Office: 855 Days
• Field of Search: 711/5, 711/203, 711/206, 711/105
• US Class Current: 711/5
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.

Claims

1. A design method for providing a flexible memory controller wherein the memory controller interfaces a host processor to a cache memory for improving a data bandwidth therebetween, the cache memory having a first and a second memory, the memory controller receiving operations and logical addresses from the host processor and providing memory control signals and physical addresses to the cache memory, the design method comprising steps of:

(a) designing a memory instruction processor, prior to identifying a memory technology for the first and the second memory, for receiving the operations and the logical addresses, translating the operations into generic memory instructions, and converting the logical addresses into memory system addresses;

(b) designing a dataflow block for error checking and correcting (ECC) and sparing, the dataflow block coupled between the cache memory and the host processor and being controlled by said memory instruction processor;

(c) identifying a first memory technology for the first memory;

(d) designing a first memory instruction decoder coupled between said memory instruction processor and said first memory for accessing said first memory and decoding the generic memory instructions into control signals specific to said first memory technology and converting the memory system addresses into physical addresses specific to said first memory;

(e) identifying a second memory technology for the second memory, said second memory technology different from said first memory technology; and

(f) designing a second memory instruction decoder coupled between said memory instruction processor and said second memory for accessing said second memory and decoding the generic memory instructions into control signals specific to said second memory technology and converting the memory system addresses into physical addresses specific to said second memory.

2. The design method according to claim 1 wherein the step (a) includes designing a performance manager, the performance manager converting the operations from the host processor into the generic memory instructions, the instructions not being specific to a particular memory technology.

3. The design method according to claim 1 wherein step (a) includes designing an address checker wherein the address checker ensures that the logical addresses are within a predetermined range.

4. The design method according to claim 1 wherein the step (a) includes designing an address translator, said address translator converting the logical addresses into memory addresses.

5. The design method according to claim 1, wherein the step (d) includes designing a row/column address translator for providing row and column address signals to the first memory.

6. The design method according to claim 1 wherein the step (f) includes designing a row/column address translator for providing row and column address signals to the second memory.

7. The design method according to claim 6 further comprising a step (g) of integrating the memory instruction processor, the dataflow block, and the first memory instruction decoder onto a single semiconductor integrated circuit.

8. The design method according to claim 1 wherein the first memory technology is a dynamic random access memory (DRAM) technology.

9. The design method according to claim 1 wherein the second memory technology is a synchronous dynamic random access memory (SDRAM) technology.

10. A memory controller for interfacing a cache memory to a host processor for increasing a data bandwidth therebetween, the cache memory having a first and second memory type, the first memory type characterized by a first memory technology and the second memory type characterized by a second memory technology different from the first memory technology, said memory controller receiving host commands and logical addresses from said host processor for accessing the cache memory, said memory controller comprising:

a memory instruction processor for receiving the host commands and logical addresses, said memory instruction processor converting said host commands into generic memory instructions and said logical addresses into memory system addresses, said memory system addresses corresponding to one of said memory types;

a dataflow block coupled between the cache memory and the host processor for providing data control, error checking and correcting, and sparing;

a first memory instruction decoder, de-embedded from said memory instruction processor, said first memory instruction decoder translating the memory system addresses into physical addresses of said first memory type and converting the generic memory instructions into control signals specific to the first memory technology; and

a second memory instruction decoder, de-embedded from said memory instruction processor, said second memory instruction decoder translating the memory system addresses into physical addresses of said second memory type and converting the generic memory instructions into control signals specific to the second memory technology.

11. The memory controller according to claim 10 wherein the first memory type is a dynamic random access memory (DRAM), and the first memory technology is a DRAM technology.

12. The memory controller according to claim 10 wherein the second memory type is a synchronous dynamic random access memory (SDRAM), and the second memory technology is a SDRAM technology.

13. The memory controller of claim 10 wherein said memory instruction processor looks ahead for a cache row hit to avoid unnecessary row precharging.

14. The memory controller of claim 10 wherein said memory instruction processor receives a data request command from said host processor, instructs said first memory instruction decoder to access only said physical addresses in said first memory type storing a portion of the requested data, and instructs said second memory instruction decoder to access only said physical addresses in said second memory type storing a remaining portion of the requested data.

15. A data processing system having a customizable memory controller, said data processing system comprising:

a host processor;

a cache memory including a first memory type comprising a first memory technology and a second memory type comprising a second memory technology; and

said memory controller for interfacing the cache memory to a host processor for increasing a data bandwidth therebetween, said memory controller receiving host operations and logical addresses from said host processor for accessing said cache memory, said memory controller comprising;

a memory instruction processor for converting said host operations to generic memory instructions and said logical addresses to memory system addresses, said memory system addresses corresponding to one of said memory types, said memory instruction processor identifying row hits for improving cache memory access speed;

a dataflow block coupled between the cache memory and the host processor for providing data control, error checking and correcting, and sparing, said dataflow block clocking data transferred between the host processor and the cache memory;

a first memory instruction decoder, de-embedded from said memory instruction processor, said first memory instruction decoder translating said memory system addresses into physical addresses of said first memory type and converting the generic memory instructions into control signals specific to said first memory technology; and

a second memory instruction decoder, de-embedded from said memory instruction processor, said second memory instruction decoder translating said memory system addresses into physical addresses of said second memory type and converting the generic memory instructions into control signals specific to said second memory technology.

16. The data processing system of claim 15 wherein said first memory type is a dynamic random access memory (DRAM), and said first memory technology is a DRAM technology.

17. The data processing system of claim 15 wherein said second memory type is a synchronous dynamic random access memory (SDRAM), and said second memory technology is a SDRAM technology.

18. A method, in a cache memory controller, for interfacing a cache memory to a host processor such that data bandwidth is increased therebetween, said cache memory having a first and second memory type, said first memory type characterized by a first memory technology and said second memory type characterized by a second memory technology different from the first memory technology, said cache memory controller coupled between said host processor and said cache memory, said method comprising steps of:

(a) receiving host commands and logical addresses from said host processor in a memory instruction processor;

(b) said memory instruction processor converting said host commands into generic memory instructions and said logical addresses into memory system addresses, said memory system addresses corresponding to one of said memory types;

(c) translating said memory system addresses into physical addresses of said first memory type using a first memory instruction decoder, said first memory instruction decoder de-embedded from said memory instruction processor, said first memory instruction decoder also converting said generic memory instructions into control signals specific to said first memory technology; and

(d) translating said memory system addresses into physical addresses of said second memory type using a second memory instruction decoder, said second memory instruction decoder de-embedded from said memory instruction processor, said second memory instruction decoder also converting said generic memory instructions into control signals specific to said second memory technology.

19. The method of claim 18 wherein the first memory type is a dynamic random access memory (DRAM), and the first memory technology is a DRAM technology.

20. The method of claim 18 wherein the second memory type is a synchronous dynamic random access memory (SDRAM), and the second memory technology is a SDRAM technology.

21. The method of claim 18 further comprising step of:

(e) providing data control, error checking and correcting, and sparing using a dataflow block.