Phase locked loop including a sampling circuit for reducing spurious side bands

• US 5,920,233 A
• Filed: 11/18/1996
• Issued: 07/06/1999
• Est. Priority Date: 11/18/1996
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Denny, Paul A.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/751,571
• Time in Patent Office: 960 Days
• Field of Search: 331/14, 331/17, 331/25, 331/DIG. 2
• US Class Current: 331/14
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

An apparatus and method for reducing spurious sidebands in the tuning signal of phase locked loop frequency synthesizers and phase locked loops is disclosed. The frequency synthesizer includes an oscillator, a divider, a difference circuit and a sampling circuit. The oscillator produces a variable frequency oscillator signal in response to an applied tuning signal. The divider divides the variable frequency oscillator signal by a division factor to produce a reduced frequency signal. The difference circuit receives the reduced frequency signal to produce a difference signal corresponding to the phase difference between the reference signal and the reduced frequency signal. The sampling circuit intermittently samples the difference signal in response to a timing signal to produce a tuning signal which approaches a DC characteristic. The tuning signal serves to adjust the oscillator frequency in a direction to diminish phase differences in the reference signal and the reduced frequency signal. In another aspect of the invention, a PLL is disclosed with the sampling circuitry for intermittently sampling the difference signal in response to a timing signal.

Claims

1. A frequency synthesizer, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a divider circuit which divides by a division factor and communicating with said oscillator to receive and divide said variable frequency oscillator signal by said division factor to produce a reduced frequency signal;

a difference circuit to receive a reference signal and said reduced frequency signal and to produce a difference signal corresponding to an accumulation of phase differences of the reference signal and the reduced frequency signal; and

a sample circuit which samples the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

2. The frequency synthesizer of claim 1, wherein said difference circuit further comprises:

a phase comparator to receive the reference signal and the reduced frequency signal to produce a phase signal corresponding to phase differences of the reference signal and the reduced frequency signal; and

an integrator to receive and cumulatively integrate the phase signal to produce the difference signal.

3. The frequency synthesizer of claim 2, wherein said sample circuit further comprises:

a null detect circuit to receive the phase signal, to detect a null in the phase signal and to produce the timing signal.

4. The frequency synthesizer of claim 1, wherein said sample circuit further comprises:

an antisaturation circuit to receive the difference signal, to detect a threshold condition on the difference signal, and to produce a lock signal; and

wherein

said sample circuit samples the difference signal in response to at least one of the timing signal and the lock signal to produce the tuning signal.

5. The frequency synthesizer of claim 1, wherein:

said divider circuit further comprises;

a) a fractional control to provide a cycle signal corresponding to a changeover between at least two division factors;

b) a fractional divider to divide the variable frequency oscillator signal by each of the at least two division factors in response to the cycle signal to produce the reduced frequency signal which is a non-integer fraction of the oscillator signal.

6. A phase locked loop, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a difference circuit to receive a reference signal and said variable frequency oscillator signal and to produce a difference signal corresponding to an accumulation of phase differences of the reference signal and the variable frequency oscillator signal; and

a sample circuit which samples the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

7. The phase locked loop of claim 6, wherein said difference circuit further comprises:

a phase comparator to receive the reference signal and the variable frequency oscillator signal to produce a phase signal corresponding to phase differences of the reference signal and the variable frequency oscillator signal; and

an integrator to receive and cumulatively integrate the phase signal to produce the difference signal.

8. The phase locked loop of claim 7, wherein said sample circuit further comprises:

a null detect circuit to receive the phase signal, to detect a null in the phase signal and to produce the timing signal.

9. The phase locked loop of claim 6, wherein said sample circuit further comprises:

an antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal; and

said sample circuit samples the difference signal in response to at least one of the timing signal and the lock signal to produce the tuning signal.

10. A frequency synthesizer, comprising:

an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;

a divider comprising an input lead coupled to the output lead of the oscillator and an output lead, responsive to the oscillator signal at the divider input lead to generate a reduced frequency signal at the divider output lead;

a difference circuit comprising a first input lead coupled to the output lead of the divider, a second input lead and an output lead, and said difference circuit responsive to the reduced frequency signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the reduced frequency signal; and

a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

11. The frequency synthesizer of claim 10, wherein:

said difference circuit further comprises;

a) a phase comparator comprising first and second input leads coupled to the first and second input leads of the difference circuit and an output lead, and responsive to the reduced frequency signal on the difference circuit first input lead and the reference signal on the difference circuit second input lead to generate a phase signal at said phase comparator output lead, such that the phase signal corresponds to a cumulation of phase differences of the reference signal and the reduced frequency signal; and

b) an integrator comprising an input lead coupled to the output lead of the phase comparator and an output lead coupled to the output lead of the difference circuit and responsive to the phase signal at the integrator input lead to cumulatively integrate the phase signal and to generate the difference signal at the difference circuit output lead.

12. The frequency synthesizer of claim 11, wherein said sample circuit further comprises:

a) a null detect circuit comprising an input lead coupled to said output lead of said phase comparator and an output lead, responsive to a null in the phase signal on the null detect circuit input lead to generate the timing signal at the output lead of the null detect circuit.

13. The frequency synthesizer of claim 10, wherein said sample circuit further comprises:

an antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit; and

the sample circuit is further responsive to at least one of the timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

14. The frequency synthesizer of claim 11, wherein:

said divider further comprises;

a) a fractional divider comprising, a first input lead coupled to the input lead of the divider, an output lead coupled to the output lead of the divider and a second input lead, responsive to the oscillator signal at the first input lead and a cyclic signal at the second input lead of the fractional divider to divide the oscillator signal by each of at least two division factors to generate the reduced frequency signal at the divider output lead; and

b) a fractional control logic comprising an input lead coupled to the output lead of the divider and an output lead coupled to the second input lead of the fractional divider, responsive to the reduced frequency signal at the fractional control logic input lead to produce the cyclic signal at the fractional control logic output lead, whereby said reduced frequency signal is a non-integer fraction of said oscillator signal; and

the sample circuit further comprises;

a) a switch circuit comprising an output lead coupled to said second input lead of said sample circuit and an input lead, and responsive to the cyclic signal and the phase signal on the switch circuit input lead to generate the timing signal at the output lead of the switch circuit.

15. A phase locked loop, comprising:

an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;

a difference circuit comprising a first input lead coupled to the output lead of the oscillator, a second input lead and an output lead, and said difference circuit responsive to the oscillator signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the oscillator signal; and

a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

16. The phase locked loop of claim 15, wherein said difference circuit further comprises:

a) a phase comparator comprising first and second input leads coupled to the first and second input leads of the difference circuit and an output lead, and responsive to the oscillator signal on the difference circuit first input lead and the reference signal on the difference circuit second input lead to generate a phase signal at said phase comparator output lead, such that the phase signal corresponds to phase differences of the reference signal and the oscillator signal; and

b) an integrator comprising an input lead coupled to the output lead of the phase comparator and an output lead coupled to the output lead of the difference circuit and responsive to the phase signal at the integrator input lead to cumulatively integrate the phase signal and to generate the difference signal at the difference circuit output lead.

17. The phase locked loop of claim 16, wherein said sample circuit further comprises:

a) a null detect circuit comprising an input lead coupled to the output lead of the phase comparator and an output lead, responsive to a null in the phase signal on the null detect circuit input lead to generate the timing signal at the output lead of the null detect circuit.

18. The phase locked loop of claim 15, wherein said sample circuit further comprises:

an antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit; and

said sample circuit is responsive to at least one of the timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

19. A method for operating a frequency synthesizer, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

dividing the oscillator signal by a division factor to generate a reduced frequency signal;

combining a reference signal and the reduced frequency signal to generate a difference signal proportional to an accumulation of phase differences between the reference signal and the reduced frequency signal; and

sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

20. The method of claim 19, wherein the step of combining further comprises:

a) detecting phase differences between the reference signal and the reduced frequency signal to generate a phase signal; and

b) cumulatively integrating the phase signal to produce the difference signal.

21. The method of claim 20, wherein the step of sampling further comprises:

a) detecting a null in the phase signal to generate the timing signal.

22. The method of claim 19, wherein the step of sampling further comprises:

a) detecting a threshold condition on the difference signal, and generating a lock signal; and

b) sampling the difference signal in response to at least one of the timing signal and the lock signal to generate the tuning signal.

23. The method of claim 20, wherein:

the step of dividing further comprises;

a) generating a cyclic signal corresponding to the cyclic alteration of at least two division factors; and

b) dividing the oscillator signal by each of at least two division factors in response to the cyclic signal to generate the reduced frequency signal, such that the reduced frequency signal is a non-integer fraction of the oscillator signal; and

the step of sampling further comprises;

a) detecting the cyclic signal and the phase signal to generate the timing signal.

24. A method for operating a phase locked loop, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

combining a reference signal and the oscillator signal to generate a difference signal proportional to an accumulation of phase differences between the reference signal and the oscillator signal; and

sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

25. The method of claim 24, wherein the step of combining further comprises:

detecting phase differences between the reference signal and the oscillator signal to generate a phase signal; and

cumulatively integrating the phase signal to produce the difference signal.

26. The method of claim 25, wherein the step of sampling further comprises:

detecting a null in the phase signal to generate the timing signal.

27. The method of claim 24, wherein the step of sampling further comprises:

detecting a threshold condition on the difference signal, and producing a lock signal; and

sampling the difference signal in response to at least one of the timing signal and the lock signal to generate the tuning signal.

28. A difference circuit, comprising:

a phase comparator to receive a first signal and a second signal to produce a phase difference signal corresponding to phase differences of the first and the second signal; and

an integrator to continuously receive and integrate the phase difference signal to produce a difference signal corresponding to an accumulation of the phase differences of the first and the second signal;

a sample circuit which samples the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences; and

a hold circuit to hold the sampled difference signal and produce a tuning signal, corresponding to the sampled difference signal.

29. The difference circuit of claim 28, wherein said timing signal corresponds to a null in said phase difference signal.

30. The difference circuit of claim 28, further comprising;

an oscillator for producing the first signal having a frequency varying in response to the tuning signal.

31. A method for operating a difference circuit, comprising:

combining a first signal and a second signal to generate a phase difference signal corresponding to phase differences of the first and the second signal; and

integrating the phase difference signal to produce a difference signal corresponding to an accumulation of the phase differences of the first and the second signal;

sampling the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences; and

holding the sampled difference signal; and

generating a tuning signal, corresponding to the sampled difference signal.

32. The method of claim 31 wherein the step of sampling further comprises:

a) detecting a null in the phase difference signal to generate the timing signal.

33. The method of claim 31, further comprising:

generating the second signal having a frequency corresponding to the tuning signal.

34. A frequency synthesizer, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a divider circuit which divides by a division factor and said divider circuit communicating with a reference signal source to receive a reference signal and to divide the reference signal by the division factor to produce a reduced frequency signal;

a difference circuit to receive said variable frequency oscillator signal and to communicate with said divider circuit to receive said reduced frequency signal to produce a difference signal corresponding to an accumulation of phase differences of the variable frequency oscillator signal and the reduced frequency signal; and

a sample circuit which samples the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

35. The frequency synthesizer of claim 34, wherein said difference circuit further comprises:

a phase comparator to receive the variable frequency oscillator signal and the reduced frequency signal to produce a phase signal corresponding to phase differences of the variable frequency oscillator signal and the reduced frequency signal; and

an integrator to receive and cumulatively integrate the phase signal to produce the difference signal.

36. The frequency synthesizer of claim 35, wherein said sample circuit further comprises:

a null detect circuit to receive the phase signal, to detect a null in the phase signal and to produce the timing signal.

37. The frequency synthesizer of claim 34, wherein said sample circuit further comprises:

an antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal; and

said sample circuit samples the difference signal in response to at least one of the timing signal and the lock signal to produce the tuning signal.

38. The frequency synthesizer of claim 34, wherein:

said divider circuit further comprises;

a) a fractional control to provide a cycle signal corresponding to a changeover between at least two division factors;

b) a fractional divider to divide said reference signal by each of the at least two division factors in response to the cycle signal to produce the reduced frequency signal which is a non-integer fraction of said reference signal.

39. A method for operating a frequency synthesizer, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

dividing a reference signal by a division factor to generate a reduced frequency signal;

combining the oscillator signal and the reduced frequency signal to generate a difference signal proportional to an accumulation of phase differences between the oscillator signal and the reduced frequency signal; and

sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

40. The method of claim 39, wherein the step of combining further comprises:

a) detecting phase differences between the oscillator signal and the reduced frequency signal to generate a phase signal; and

b) cumulatively integrating the phase signal to produce the difference signal.

41. The method of claim 40, wherein the step of sampling further comprises:

a) detecting a null in the phase signal to generate the timing signal.

42. The method of claim 39, wherein the step of sampling further comprises:

a) detecting a threshold condition on the difference signal, and generating a lock signal; and

b) sampling the difference signal in response to at least one of the timing signal and the lock signal to generate the tuning signal.

43. The method of claim 39, wherein:

the step of dividing further comprises;

a) generating a cyclic signal corresponding to the cyclic alteration of at least two division factors; and

b) dividing the reference signal by at least two division factors responsive to the cyclic signal to generate the reduced frequency signal, such that the reduced frequency signal is a non-integer fraction of the reference signal; and

the step of sampling further comprises;

a) detecting the difference signal and the cyclic signal to generate the timing signal.

44. A frequency synthesizer, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a divider circuit which divides by a division factor and communicating with said oscillator to receive and divide said variable frequency oscillator signal by the division factor to produce a reduced frequency signal;

a difference circuit to receive a reference signal and said reduced frequency signal to produce a difference signal corresponding to a phase difference of the reference signal and the reduced frequency signal; and

a sample circuit including an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on the difference signal, and to produce a lock signal, and said sample circuit sampling the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

45. A phase locked loop, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a difference circuit to receive a reference signal and said variable frequency oscillator signal to produce a difference signal corresponding to a cumulation of phase differences of the reference signal and the variable frequency oscillator signal; and

a sample circuit including an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal, and said sample circuit to sample the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

46. A frequency synthesizer, comprising:

an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;

a divider comprising an input lead coupled to the output lead of the oscillator and an output lead, responsive to the oscillator signal at the divider input lead to generate a reduced frequency signal at the divider output lead;

a difference circuit comprising a first input lead coupled to the output lead of the divider, a second input lead and an output lead, and said difference circuit responsive to the reduced frequency signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to a cumulation of phase differences of the reference signal and the reduced frequency signal; and

a sample circuit including an antisaturation circuit, and the sample circuit comprising a first input lead and a second input lead, the first input lead being coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and the antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit, and the sample circuit responsive to at least one of a timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

47. A method for operating a frequency synthesizer, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

dividing the oscillator signal by a division factor to generate a reduced frequency signal;

combining a reference signal and the reduced frequency signal to generate a difference signal proportional to a cumulation of phase differences between the reference signal and the reduced frequency signal;

detecting a threshold condition on the difference signal, and generating a lock signal; and

sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

48. A method for operating a phase locked loop, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

combining a reference signal and the oscillator signal to generate a difference signal proportional to a cumulation of phase differences between the reference signal and the oscillator signal;

detecting a threshold condition on the difference signal, and producing a lock signal; and

sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

49. A frequency synthesizer, comprising:

an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;

a divider circuit which divides by a division factor and said divider circuit communicating with a reference signal source to receive a reference signal and to divide the reference signal by the division factor to produce a reduced frequency signal;

a difference circuit to receive said variable frequency oscillator signal and to communicate with said divider circuit to receive said reduced frequency signal to produce a difference signal corresponding to a cumulation of phase differences of the variable frequency oscillator signal and the reduced frequency signal; and

a sample circuit which includes an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal, and the sample circuit to sample the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

50. A method for operating a frequency synthesizer, comprising:

generating an oscillator signal having a frequency corresponding to a tuning signal;

dividing a reference signal by a division factor to generate a reduced frequency signal;

combining the oscillator signal and the reduced frequency signal to generate a difference signal proportional to a cumulation of phase differences between the oscillator signal and the reduced frequency signal;

detecting a threshold condition on the difference signal, and generating a lock signal; and

sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

51. A phase locked loop, comprising:

an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;

a difference circuit comprising a first input lead coupled to the output lead of the oscillator, a second input lead and an output lead, and said difference circuit responsive to the oscillator signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the oscillator signal;

a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead; and

wherein said sample circuit further comprises;

an antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit; and

said sample circuit second input lead is responsive to at least one of the timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.