CMOS image sensor with improved fill factor

• US 5,920,345 A
• Filed: 06/02/1997
• Issued: 07/06/1999
• Est. Priority Date: 06/02/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Sauer, Donald Jon
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): MOE, AUNG SOE
• Application Number:
  US08/867,577
• Time in Patent Office: 764 Days
• Field of Search: 348/308, 348/303, 348/304, 348/302, 348/311, 348/309, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

An active pixel sensor circuit and method. According to one embodiment, a photodetector produces a voltage at a floating diffusion node in accordance with light sensed by the photodetector. An active element is coupled at a control terminal to the floating diffusion node and is directly couplable at an output terminal to an output line. The active element is configured to provide an output voltage on the output line having a magnitude related to the magnitude of the floating diffusion node voltage.

Claims

1. An active pixel sensor (APS) circuit, comprising:

(a) a photodetector which produces a node voltage at a node in accordance with light sensed by the photodetector;

(b) a first transistor coupled at a gate terminal to the node and directly coupleable at a source terminal to an output line coupled to a sample and hold circuit, wherein the first transistor is configured to operate in source follower mode to provide an output voltage on the output line having a magnitude related to the magnitude of the node voltage; and

(c) a second transistor having a source terminal coupled to the gate terminal of the first transistor, a gate terminal coupled to a phase reset signal, and a drain terminal coupled to a row voltage signal and to a drain terminal of the first transistor, wherein;

the phase reset signal switches high during times at which the charge stored in the photodetector is not being read to couple the gate terminal of the first transistor to the row voltage signal; and

the row voltage signal switches low during times at which the charge stored in the photodetector is not being read to switch off the first transistor, whereby the circuit is isolated from the output line when the charge stored in the photodetector is not being read.

2. The circuit of claim 1, wherein the output line is coupled to a current source.

3. The circuit of claim 2, wherein:

the sample and hold circuit is a correlated-double sampling (CDS) circuit; and

the CDS circuit comprises the current source coupled to the output line.

4. The circuit of claim 2, further comprising a third transistor for selectively coupling the photodetector to the node.

5. The circuit of claim 1, wherein the circuit is one of an array of APS circuits of an APS imager.

6. The circuit of claim 1, wherein the circuit is one of an array of APS circuits of an APS imager, further wherein each APS circuit of the array comprises a source follower transistor configured identically to the first transistor of the circuit and each APS circuit in the same column of the array as the circuit is coupled at the source terminal of its respective source follower transistor to the output line.

7. The circuit of claim 1, wherein the photodetector is a virtual gate buried n-channel photodetector.

8. The circuit of claim 1, wherein the node is a floating diffusion node.

9. In an APS circuit comprising (1) a photodetector which produces a node voltage at a node in accordance with light sensed by the photodetector, (2) a first transistor coupled at a gate terminal to the node and directly coupled at a source terminal to an output line coupled to a sample and hold circuit, and (3) a second transistor having a source terminal coupled to the gate terminal of the first transistor, a method comprising the steps of:

(a) switching a phase reset signal coupled to a gate terminal of the second transistor high during times at which a charge stored in the photodetector is not being read to couple the gate terminal of the first transistor to a drain terminal of the second transistor, wherein the drain terminal of the second transistor is coupled to a drain terminal of the first transistor and to a row voltage signal; and

(b) switching the row voltage signal low during times at which the charge stored in the photodetector is not being read to switch off the first transistor, whereby the circuit is isolated from the output line, wherein, when the charge stored in the photodetector is being read, the first transistor is configured to operate in source follower mode to provide an output voltage on the output line having a magnitude related to the magnitude of the node voltage.

10. The method of claim 9, further comprising the step of applying a current source to the output line.

11. The method of claim 9, wherein the node is a floating diffusion node.

12. An image sensor, comprising an array of APS circuits, each APS circuit of the array comprising:

(1) a photodetector which produces a node voltage at a node in accordance with light sensed by the photodetector;

(2) a first transistor coupled at a gate terminal to the node and directly coupleable at a source terminal to a column output line for the array column for said each APS circuit, wherein said column output line is coupled to a sample and hold circuit, further wherein the first transistor is configured to operate in source follower mode to provide an output voltage on the column output line having a magnitude related to the magnitude of the node voltage; and

(3) a second transistor having a source terminal coupled to the gate terminal of the first transistor, a gate terminal coupled to a phase reset signal, and a drain terminal coupled to a row voltage signal and to a drain terminal of the first transistor, wherein;

the phase reset signal switches high during times at which the charge stored in the photodetector is not being read to couple the gate terminal of the first transistor to the row voltage signal; and

the row voltage signal switches low during times at which the charge stored in the photodetector is not being read to switch off the first transistor, whereby the circuit is isolated from the column output line when the charge stored in the photodetector is not being read.

13. The image sensor of claim 12, further comprising a row of CDS circuits having one CDS circuit for each column of the array of APS circuits, wherein each said CDS circuit is coupled to the column output line for the corresponding column of the array of APS circuits.

14. In an image sensor comprising an array of APS circuits, wherein each APS circuit of the array comprises (1) a photodetector which produces a node voltage at a node in accordance with light sensed by the photodetector, (2) a first transistor coupled at a gate terminal to the node and directly coupled at a source terminal to a column output line for the array column for said each APS circuit, said column output line being coupled to a sample and hold circuit, and (3) a second transistor having a source terminal coupled to the gate terminal of the first transistor, a method comprising the steps of column output line for the array column for said each APS circuit, a method comprising the step of:

(a) switching a phase reset signal coupled to a gate terminal of the second transistor high during times at which a charge stored in the photodetector is not being read to couple the gate terminal of the first transistor to a drain terminal of the second transistor, wherein the drain terminal of the second transistor is coupled to a drain terminal of the first transistor and to a row voltage signal; and

(b) switching the row voltage signal low during times at which the charge stored in the photodetector is not being read to switch off the first transistor, whereby the at least one APS circuit is isolated from the column output line, wherein, when the charge stored in the photodetector is being read, the first transistor is configured to operate in source follower mode to provide an output voltage on the output line having a magnitude related to the magnitude of the node voltage.

15. The method of claim 14, further comprising the step of applying a current source to the column output line.

16. The method of claim 14, wherein the image sensor further comprises a row of CDS circuits having one CDS circuit for each column of the array of APS circuits, wherein each said CDS circuit is coupled to the column output line for the corresponding column of the array of APS circuits.