Method of fabricating a self-aligned silicide MOSFET
First Claim
1. A method of fabricating a MOSFET device, comprising the sequential steps of:
- providing a substrate, wherein a gate is on the substrate;
forming an oxide layer on the substrate, and implanting the substrate with first ions;
forming a first depositing layer;
etching the first depositing layer to form a first spacer, and implanting the substrate with second ions;
forming a second depositing layer;
etching the second depositing layer to form a second spacer alongside the first spacer;
etching the oxide layer to expose part of the side walls of the gate; and
forming a metal silicide layer by a self-aligned process by depositing a metal layer so that the metal layer contacts said exposed part of the sidewall of the gate.
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Abstract
A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.
78 Citations
24 Claims
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1. A method of fabricating a MOSFET device, comprising the sequential steps of:
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providing a substrate, wherein a gate is on the substrate; forming an oxide layer on the substrate, and implanting the substrate with first ions; forming a first depositing layer; etching the first depositing layer to form a first spacer, and implanting the substrate with second ions; forming a second depositing layer; etching the second depositing layer to form a second spacer alongside the first spacer; etching the oxide layer to expose part of the side walls of the gate; and forming a metal silicide layer by a self-aligned process by depositing a metal layer so that the metal layer contacts said exposed part of the sidewall of the gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification
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- Resources
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Current AssigneeUnited Microelectronics Corporation
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Original AssigneeUnited Microelectronics Corporation
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InventorsTseng, H. C., Huang, Heng-Sheng, Chen, Kun-Cho
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Primary Examiner(s)Booth, Richard A.
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Application NumberUS09/055,692Time in Patent Office456 DaysField of Search438/592, 438/305, 257/413US Class Current438/305CPC Class CodesH01L 21/28052 the conductor comprising a ...H01L 21/28518 the conductive layers compr...H01L 29/665 using self aligned silicida...H01L 29/66507 providing different silicid...H01L 29/6656 using multiple spacer layer...H01L 29/6659 with both lightly doped sou...Y10S 257/90 MOSFET type gate sidewall i...
