Two phase low energy signal processing using charge transfer capacitance

• US 5,923,204 A
• Filed: 11/06/1997
• Issued: 07/13/1999
• Est. Priority Date: 11/08/1996
• Status: Expired due to Fees

• Current Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Rapeli, Juha, De Albuquerque Epifanio Da Franca, Jose, De Almeida De Azeredo Leme, Carlos Mexia, Dos Santos Reis, Ricardo, Zuna Bello, Joao Paulo, De Sousa Cardoso Lopes, Pedro Antonio
• Primary Examiner(s): Callahan, Tim
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/965,544
• Time in Patent Office: 614 Days
• Field of Search: 327/337, 327/336, 327/554, 327/536, 327/537, 327/589
• US Class Current: 327/337
• CPC Class Codes: G06G 7/184 using capacitive elements

Abstract

A charge transfer from signal voltage (U_S) to integrating capacitance (C_O) is accomplished by means of charge transfer capacitance (C_i), an active element (T) and controllable switches (S₆₁, S₆₂, S₆₃, S₆₄). The operation of the circuit is additionally based on the fact that the charge transfer to the charge transfer capacitance (C_i) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by a constant-current element set. These features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.

Claims

1. A method for processing a signal (U_S) wherein

in a first phase, a charge transfer capacitance (C_i) is switched into an operational connection with the signal (U_S),

the charge of the charge transfer capacitance (C_i) is changed by a charge amount which is proportional to an instantaneous value of the signal (U_S) being processed during said first phase,

in a second phase, the charge transfer capacitance (C_i) is switched into an operational connection with an integrating capacitance (C_O),

at least a portion of the charge of the charge transfer capacitance (C_i) is transferred from the charge transfer capacitance (C_i) to said integrating capacitance (C_O) during the second phase and

the charge of said charge transfer capacitance (C_i), established in said first phase, is changed by current formed by an active element (T) connected to the charge transfer capacitance (C_i) and this current has been arranged to be dependent on the charge of said charge transfer capacitance (C_i),

characterized in that

said charge transfer from said charge transfer capacitance (C_i) to said integrating capacitance (C_O) occurs by means of a difference between the currents of the active element (T) and of a constant-current element (I_c) connected in series with said active element (T), in such a way that said difference current flows essentially through the charge transfer capacitance (C_i) changing said

charge by the amount which is proportional to the instantaneous value of the signal (U_S).

2. A method according to claim 1, further characterized in that the current of said active element (T) is controlled by said signal (U_S).

3. A method according to claim 1, further characterized in that the current of the active element (T) is controlled on the basis of the charge transfer capacitance (C_i) and that said current reverts essentially to zero after the charge in said transfer capacitance (C_i) has been transferred to the integrating capacitance (C_O).

4. A method according to claim 1, further characterized in that the current changing the charge of said charge transfer capacitance (C_i) is essentially the difference between the current formed by said active element (T) and the current formed by said constant-current element (I_c).

5. A method according to claim 1, further characterized in that the charge change in the charge transfer capacitance (C_i), resulting from the charge of said transfer capacitance (C_i) being transferred from the charge transfer capacitance (C_i) to the integrating capacitance (C_O), is proportional to the signal (U_S) of the charge transfer capacitance (C_i) resulting from said first phase and is opposite in sign.

6. A circuit arrangement for processing a signal (U_S) in a first phase and a second phase, said circuit comprising:

a charge transfer capacitance (C_i) having first and second poles,

an active element (T) connected to said first pole of said charge transfer capacitance (C_i),

first switching elements (S₆₁, S_S63) for switching, in the first phase, the charge transfer capacitance (C_i) into an operational connection with the signal (U_S) through said active element (T) for changing a charge of said charge transfer capacitance (C_i) by a charge amount which is proportional to an instantaneous value of the signal (U_S),

an integrating capacitance (C_O) switchably connected to said second pole of said charge transfer capacitance (C_i),

second switching elements (S₆₂, S₆₄) for switching, in the second phase, the charge transfer capacitance (C_i) into an operational connection with said integrating capacitance (C_O) for transferring at least a portion of the charge from the charge transfer capacitance (C_i) to the integrating capacitance (C_O),

said active element (T) changing the charge of the charge transfer capacitance (C_i) depending on the charge of said charge transfer capacitance (C_i), and

characterized in that said circuit further comprises;

a constant-current element (I_c) for changing the charge of the charge transfer capacitance (C_i) in which case said active element (T) and said constant-current element (I_c) are connected in series so that a difference between the currents they form flows essentially through the charge transfer capacitance (C_i), changing its charge by said amount which is proportional to the instantaneous value of the signal (U_S).

7. A circuit arrangement according to claim 6, further characterized in that in the first phase said first switching elements (S₆₁, S₆₃) have been arranged to switch said signal (U_S) to an input (G,S) of said active element (T) to ensure that said difference between the currents formed by the active element (T) and the constant current element (I_c) is dependent on the instantaneous value of said signal (U_S).

8. A circuit arrangement according to claim 6, further characterized in that in said first phase said first switching elements (S₆₁, S₆₃) have been arranged to connect the second pole of the charge transfer capacitance (C_i) to a constant potential (V_r).

9. A circuit arrangement according to claim 8, further characterized in that one pole of said integrating capacitance (C_O) is connected to said constant potential (V_r).

10. A circuit arrangement according to claim 6, further characterized in that in said second phase said second switching elements (S₆₂, S₆₄) have been arranged to connect said charge transfer capacitance (C_i) and said integrating capacitance (C_O) in series for transferring the charge of the charge transfer capacitance (C_i), resulting from phase one, between said capacitances (C_i, C_O).

11. A circuit arrangement according to claim 6, further characterized in that in said second phase, said second switching elements (S₆₂, S₆₄) have been arranged to connect said charge transfer capacitance (C_i) to an input (G, S) of the active element (T) to ensure that the current formed by the active element (T) is dependent on the charge of said charge transfer capacitance (C_i).

12. A circuit arrangement according to claim 6, further characterized in that the active element (T) comprises a gate (G), a source (S) and a drain (D) such that the drain (D) of the active element (T) is connected to a first supply voltage (V_DD), the source (S) of the active element (T) is connected to the first pole of the charge transfer capacitance (C_i), and the gate (G) receives signal (U_S).

13. A circuit arrangement according to claim 6, further characterized in that said constant-current element (I_c) is connected between the first pole of said charge transfer capacitance (C_i) and a second supply voltage (V_SS).