DSS/DVD picture in picture with internet

• US 5,923,379 A
• Filed: 12/02/1996
• Issued: 07/13/1999
• Est. Priority Date: 12/02/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Patterson, James T.
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US08/759,111
• Time in Patent Office: 953 Days
• Field of Search: 348/564, 348/565, 348/566, 348/567, 348/568, 348/569, 348/584, 348/586, 348/588, 348/598, 348/599, 348/589, 348/600
• US Class Current: 725/70
• CPC Class Codes: H04N 21/4135 external recorder interface circuits between an apparatus for recording television signals and a television receiver H04N5/775
• CPC Class Codes: H04N 21/42676 for modulating an analogue carrier signal to encode digital information or demodulating it to decode digital information, e.g. ADSL or cable modem
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/4782 Web browsing , e.g. WebTV
• CPC Class Codes: H04N 21/6125 involving transmission via Internet transmission by internet of broadcast information H04H60/82
• CPC Class Codes: H04N 21/6143 involving transmission via a satellite
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen

Abstract

A system for providing a user controllable picture-in-picture formatted signal to a television is provided with a fast modem that interconnects the system with a computer network, such as the Internet. In order to allow a user to interact with the Internet, yet still enjoy video programming, the system has a picture-in-picture selection that a user controls to determine which video source (e.g., digital satellite signal, digital video disk signal, Internet graphics) will form the main picture displayed on the television, and which will form the picture-in-picture. A conventional television may be used with the system to display the signal, since it is already formatted in a picture-in-picture format at the output of the system.

Claims

1. A system for providing a display signal to a single input of a television for on-screen display, comprising:

a first source of video signals;

a second source of video signals;

a picture-in-picture (PIP) processor coupled to the first and second sources and selectively formatting the first source video signals and the second source video signals to form the display signal.

2. The system of claim 1, wherein the first source of video signals is a computer network.

3. The system of claim 2, wherein the computer network is the Internet.

4. The system of claim 2, wherein the second source of video signals is a digital satellite system.

5. The system of claim 2, wherein the second source of video signals is a digital video disc player.

6. The system of claim 1, further comprising a microprocessor that controls the PIP processor in response to user input.

7. The system of claim 6, further comprising a graphics controller coupled to the microprocessor to generate graphics from the first source of video signals.

8. The system of claim 1, wherein the PIP processor comprises an RGB to YCrCb converter, a horizontal decimater, a vertical decimater, and a selection arrangement that selects which of the video signals is horizontally and vertically decimated to form a reduced picture and which of the video signals forms a normal size picture, and an output at which the video signals forming the reduced picture and the normal size picture are generated as a single picture-in-picture signal.

9. The system of claim 8, wherein the selection arrangement includes controllable multiplexers that receive the video signals from the first and second sources at multiplexer inputs and selectively provide the video signals from only one of the first or second sources at mulitplexer outputs.

10. The system of claim 9, wherein the vertical decimater includes an averaging circuit that averages a plural number of lines of a video signal.

11. The system of claim 10, wherein the averaging circuit includes a multiplier that multiplies one of the lines, and an adder that adds together the multiplied line with at least one other line to form a summation of the lines, and a divider that divides the summation to produce an averaged line.

12. The system of claim 11, wherein the number of lines that are averaged together by the averaging circuit is three.

18. The system of claim 1, wherein said single television input is an input of a TV set separate from the system, and said PIP processor provides the display signal formatted thereby, including a PIP format of said video signals from said first source and said second source, to said single television input of said separate TV set,

thereby eliminating a requirement for said TV set to have a PIP function for simultaneous display of said video signals from said first source and from said second source.

13. A picture-in-picture (PIP) processor that receives video signals from a plurality of sources and selectively formats the video signals into a display signal having a format with a first one of the video signals forming a main picture and a second one of the video signals forming a picture-in-picture, the processor comprising:

a horizontal decimater that receives the video signal that is to form the picture-in-picture and horizontally decimates said video signal;

a vertical decimater that receives the horizontally decimated video signal that is to form the picture-in-picture and vertically decimates said video signal;

a selection arrangement that selects which of the video signals is horizontally and vertically decimated to form the picture-in-picture and which of the video signals forms the main picture; and

an output at which the video signals forming the picture-in-picture and the main picture are generated as a single picture-in-picture signal.

14. A processor according to claim 13, wherein the selection arrangement includes controllable multiplexers that receive the video signals from the plurality of sources at multiplexer inputs and selectively provide the video signals from only one of the sources at mulitplexer outputs.

15. A processor according to claim 14, wherein the vertical decimater includes an averaging circuit that averages a plural number of lines of a video signal.

16. A processor according to claim 15, wherein the averaging circuit includes a multiplier that multiplies one of the lines, and an adder that adds together the multiplied line with at least one other line to form a summation of the lines, and a divider that divides the summation to produce an averaged line.

17. A processor according to claim 16, wherein the number of lines that are averaged together by the averaging circuit is three.

19. A system for providing a display signal to a TV receiver for on-screen display, comprising:

a first source of video signals;

a second source of video signals;

a picture-in-picture (PIP) processor coupled to the first and second sources and selectively formatting the first source video signals and the second source video signals to form a single display signal including therein said video signals from said first source and from said second source in PIP format,

said system providing said single display signal in PIP format to said TV receiver for display,

thereby eliminating a requirement for said TV set to have a PIP function for simultaneous display of said video signals from said first source and from said second source.

20. The system of claim 19, further comprising RF modulator means for modulating said single display signal in said PIP format to provide an RF modulated video signal in PIP format to said TV receiver.