Fault tolerant circuit arrangements

• US 5,923,512 A
• Filed: 03/12/1998
• Issued: 07/13/1999
• Est. Priority Date: 03/15/1997
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Cairns, Graham Andrew, Nomura, Toshio, Brownlow, Michael James, Kay, Andrew
• Primary Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US09/041,394
• Time in Patent Office: 488 Days
• Field of Search: 391/86, 391/78-79, 391/81, 391/87, 391/91, 391/56, 391/111, 324/522-523, 324/537, 324/765, 324/768, 324/769, 324/770
• US Class Current: 361/78
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence

Abstract

A fault tolerant circuit arrangement comprises a plurality of replicated non-redundant shift registers 30 connected in parallel and each having an enable/configuration input 31 and a plurality of outputs 36. Furthermore each register 30 includes a verify output 32 for outputting a verify signal indicating whether or not a fault condition is present within the register. The arrangement also includes a verification signal generator 33 for applying a fixed reference signal, a comparator 34 to which the verify signals from the outputs 32 are applied, and a control circuit 35. The test/control-logic of the comparator 34 and control circuit 35 is constructed using masking redundancy 20-24 in order to render the test/control logic tolerant to faults. The control circuit 35 serves to control testing of each of the registers 30 in turn by supplying an enable signal to the input 31 of each register 30 beginning with the first register. This causes the supply of a verify signal V₁ from the verify output 32 of the first register 30 to the comparator 34 which compares the verify signal V₁ to the reference signal. If the verify signal V₁ is significantly different from the reference signal, this indicates that there is a fault present in the first register, and the control circuit 35 is caused to supply a disable signal to the input 31 of the first register. The test procedure is repeated for each register 30 until a verify signal is received by the comparator 34 which indicates that there is no fault present in the associated register.

Claims

1. A fault tolerant circuit arrangement comprising:

a plurality of replicated functional circuits connected in parallel and each having an input and a plurality of outputs including a verify output; and

test/control circuit means for detecting a verify signal outputted from the verify output of each circuit in response to an input signal applied to the input of the circuit, for comparing the verify signal to a reference signal to determine whether or not a fault is present in the circuit, and for selecting for functional operation one of the circuits tested which is shown by the corresponding verify signal to be free of a fault,

wherein the test/control circuit means comprises circuit elements incorporating masking redundancy in order to render the test/control circuit means tolerant to faults.

2. A circuit arrangement according to claim 1, wherein each of the functional circuits is a shift register having an enable input for receiving an input signal and a plurality of shift outputs in parallel for outputting a functional output signal.

3. A circuit arrangement according to claim 2, wherein the verify output is constituted by one of the shift outputs of each shift register.

4. A circuit arrangement according to claim 1, wherein the test/control circuit means is arranged to sequentially detect the verify signals from the circuits and to select for functional operation the first circuit tested which is shown by the corresponding verify signal to be free of a fault.

5. An arrangement according to claim 1, wherein the test/control circuit means is arranged to apply a disable signal to the circuit in the event of the corresponding verify signal indicating that a fault is present in the circuit and to apply an enable signal to the next circuit in the sequence.

6. A circuit arrangement according claim 1, wherein a verification signature generator is provided to supply the reference signal in response to receipt of an input signal.

7. A circuit arrangement according to claim 1, wherein the test/control circuit means comprises a shift register which has a plurality of stages corresponding in number to said plurality of circuits and which is clocked so as to sequentially apply enable signals to the circuits until one of the circuits is shown to be free of a fault.

8. A circuit arrangement according to claim 1, wherein the test/control circuit means is arranged to apply an enable signal to the circuit to supply the circuit with power and to cut off the power to the circuit in the event that the corresponding verify signal outputted by the circuit indicates that a fault is present in the circuit.

9. A circuit arrangement according to claim 8, wherein the outputs of the circuit are connected to an OR gate in order to provide an output signal dependent on the output of the selected circuit and independent of the other circuits.

10. A circuit arrangement according to claim 1, wherein the test/control circuit means have a quad masking (QM) circuit architecture comprising four replicated circuit elements connected such that two pairs of elements are connected in parallel with the elements of each pair being connected in series.

11. A circuit arrangement according to claim 10, wherein a control element is connected between an interconnection point between the two elements of one pair of circuit elements and an interconnection point between the two elements of the other pair of circuit elements to control conduction between said interconnection points.

12. A circuit arrangement according to claim 11, wherein the control element is a MOSFET.

13. A liquid crystal display device comprising:

a matrix of pixels on a display substrate; and

scan and data driver circuits for driving the matrix of pixels, wherein at least one of the scan and data driver circuits includes a fault tolerant circuit including;

a plurality of replicated functional circuits connected in parallel and each having an input and a plurality of outputs including a verify output; and

test/control circuit means for detecting a verify signal outputted from the verify output of each circuit in response to an input signal applied to the input of the circuit, for comparing the verify signal to a reference signal to determine whether or not a fault is present in the circuit, and for selecting for functional operation one of the circuits tested which is shown by the corresponding verify signal to be free of a fault,

wherein the test/control circuit means comprises circuit elements incorporating masking redundancy in order to render the test/control circuit means tolerant to faults.

14. A display device according to claim 13, wherein the at least one of the driver circuits comprising the fault tolerant circuit is fabricated on the display substrate.

15. A display device according to claim 13, wherein the fault tolerant circuit is implemented using thin film transistors (TFT).