Bist architecture for measurement of integrated circuit delays
First Claim
1. An integrated circuit including:
- a plurality of circuit elements and interconnecting signal-carrying conductors;
a test bus including two test bus conductors;
a plurality of switches associated with each signal-carrying conductor, the switches selectably connecting the signal-carrying conductor to either or both of the two test bus conductors;
wherein at least two of the switches are enabled such that an oscillation circuit is formed including, in series;
one of the test bus conductors;
one of the switches;
one of;
(a) a selected path of interest through the circuit elements;
(b) a circuit which has a delay proportional to the delay through the selected path of interest; and
(c) a reference delay path having a known delay;
another of the switches;
another of the test bus conductors; and
a path with constant delay which is selectably connected between the two test bus conductors.
3 Assignments
0 Petitions
Accused Products
Abstract
A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths. A delay copier copies the delay between any two signal events, without injecting any test signal into the circuit under test (e.g. on-line test), and the delay copy can be measured by selecting it in the oscillator.
130 Citations
31 Claims
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1. An integrated circuit including:
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a plurality of circuit elements and interconnecting signal-carrying conductors; a test bus including two test bus conductors; a plurality of switches associated with each signal-carrying conductor, the switches selectably connecting the signal-carrying conductor to either or both of the two test bus conductors; wherein at least two of the switches are enabled such that an oscillation circuit is formed including, in series; one of the test bus conductors; one of the switches; one of; (a) a selected path of interest through the circuit elements; (b) a circuit which has a delay proportional to the delay through the selected path of interest; and (c) a reference delay path having a known delay; another of the switches; another of the test bus conductors; and a path with constant delay which is selectably connected between the two test bus conductors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of measuring a signal delay between any two of a plurality of terminals of an integrated circuit, the integrated circuit including two conductors selectably connected to each of the plurality of terminals, comprising the steps of:
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connecting each of two terminals of the integrated circuit to one of the two conductors; measuring a frequency of oscillation of a circuit path of interest including the two terminals and the two conductors; and comparing the measured frequency of oscillation to a measured frequency of oscillation of a reference circuit with a known delay including the two conductors and not including one of the terminals. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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Specification