Complexity determining apparatus

• US 5,933,451 A
• Filed: 10/15/1996
• Issued: 08/03/1999
• Est. Priority Date: 04/22/1994
• Status: Expired due to Term

• Current Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Girons, Regis Saint, Ozkan, Mehmet Kemal
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Liu, Shuwang
• Application Number:
  US08/727,435
• Time in Patent Office: 1,022 Days
• Field of Search: 348/405, 348/419, 348/415, 348/409, 348/402, 348/423, 348/390, 348/396, 348/518, 348/353, 386/109, 375/224, 375/247, 375/249
• US Class Current: 375/224
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/149 by estimating the code amount by means of a model, e.g. mathematical model or statistical model
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/177 the unit being a group of pictures [GOP]
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/23655 Statistical multiplexing, e.g. by controlling the encoder to alter its bitrate to optimize the bandwidth utilization
• CPC Class Codes: H04N 21/4347 Demultiplexing of several video streams

Abstract

Apparatus for determining a complexity measure of a data signal is disclosed which includes an encoder, having an input terminal responsive to a data input signal and a data output terminal producing a coded output signal representing the data input signal at a constant bit rate. The encoder includes a variable quantizer, responsive to the data input signal, for producing a quantized signal, representing the data input signal, having a quantizing step size defined in response to a quantizing step size control signal. A bit rate regulator produces the quantizing step size control signal in response to the bit rate of the coded output signal and a quota input signal. A complexity analyzer generates a complexity representative signal related to the quantizing step size and the bit rate of the coded output signal.

Claims

1. Complexity determining apparatus, comprising:

an encoder, having an input terminal responsive to a data input signal and a data output terminal producing a coded output signal representing the data input signal at a constant bit rate, and including a variable quantizer, responsive to the data input signal, for producing a quantized signal, representing the data input signal, having a quantizing step size set in response to a quantizing step size control signal;

a bit rate regulator for producing the quantizing step size control signal in response to the bit rate of the coded output signal and a quota input signal; and

a complexity analyzer, responsive to the quantizing step size control signal, and the coded output signal, for generating a complexity representative signal being related to the quantizing step size and the bit rate of the coded output signal;

wherein

the complexity analyzer generates the complexity representative signal being directly proportional to an average of the quantizing step size and to the bit rate of the coded output signal.

2. The apparatus of claim 1 wherein the complexity analyzer (16) generates the complexity representative signal (X_pic) being the product of the average of the quantizing step size () and the bit rate of the coded output signal (T_MB).

3. Complexity determining apparatus, comprising:

an encoder, having an input terminal responsive to a data input signal and a data output terminal producing a coded output signal representing the data input signal at a constant bit rate, and including a variable quantizer, responsive to the data input signal, for producing a quantized signal, representing the data input signal, having a quantizing step size set in response to a quantizing step size control signal;

a bit rate regulator for producing the quantizing step size control signal in response to the bit rate of the coded output signal and a quota input signal; and

a complexity analyzer, responsive to the quantizing step size control signal, and the coded output signal, for generating a complexity representative signal being related to the quantizing step size and the bit rate of the coded output signal;

wherein

the data signal is a video signal comprising sequential groups of pictures, each group of pictures comprising a predetermined number of sequential frames;

the encoder operates according to the motion picture experts group standard, divides each sequential frame in the video signal into a predetermined number of macroblocks, and sequentially encodes each of the predetermined number of macroblocks into respective numbers of bits to produce the coded output signal comprising a sequence of coded pictures;

the bit rate regulator produces respective quantizing step size control signals for each of the predetermined number of macroblocks; and

the complexity analyzer comprises;

a first accumulator, coupled to the data output terminal of the encoder, for summing the respective numbers of bits produced at the data output terminal of the encoder for each encoded macroblock, to produce a total number of bits in each one of the sequence of coded pictures;

a second accumulator, coupled to the bit rate regulator, for summing the respective quantizing step size control signals for each macroblock in each one of the sequential pictures;

an averaging circuit, coupled to the second accumulator, for calculating the average quantizing step size signal for the predetermined number of macroblocks in each one of the sequential pictures, to produce an average quantizing step size signal for each one of the sequence of coded pictures;

a multiplier, coupled to the first accumulator and the averaging circuit, for multiplying the total number of bits times the average quantizing step size signal, to produce a picture complexity signal for each one of the sequential pictures; and

a third accumulator for summing the respective picture complexity signals for each of the pictures in a group of pictures, to produce the complexity representative signal.