Read only memory

• US 5,943,255 A
• Filed: 03/27/1998
• Issued: 08/24/1999
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Kutter, Christoph, Tempel, Georg
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/049,558
• Time in Patent Office: 515 Days
• Field of Search: 365/94, 365/164, 365/174, 438/619
• US Class Current: 365/94
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.

Claims

1. A read only memory, comprising:

a multiplicity of conductor tracks respectively disposed in a plurality of conductor track planes including a first conductor track plane and at least one adjacent conductor track plane;

said conductor tracks of said first conductor track plane intersecting said conductor tracks of said at least one adjacent conductor track plane at intersecting regions; and

electrical contacts formed at selected intersecting regions between said conductor tracks of said first conductor track plane and of said at least one adjacent conductor track plane for representing a given logic state at the selected intersecting regions.

2. The read only memory according to claim 1, wherein said conductor tracks are metal tracks.

3. The read only memory according to claim 2, wherein said conductor tracks comprise aluminum.

4. The read only memory according to claim 1, wherein said conductor tracks are polysilicon conductor tracks.

5. The read only memory according to claim 1, wherein said electrical contacts are VIA tunnel contacts.

6. The read only memory according to claim 5, wherein said VIA tunnel contacts include a tunnel oxide formed on a lower conductor track plane and a VIA plug on said tunnel oxide.

7. The read only memory according to claim 6, wherein said VIA plug comprises tungsten.

8. The read only memory according to claim 1, which comprises intermetal oxide disposed between said conductor tracks and said conductor track planes.

9. The read only memory according to claim 8, wherein said intermetal oxide is TEOS.

10. The read only memory according to claim 1, wherein said conductor tracks of adjacent conductor track planes intersect at an angle of 90°

.

11. A method of operating a read only memory formed with a multiplicity of conductor tracks respectively disposed in a plurality of conductor track planes including a first conductor track plane and at least one adjacent conductor track plane, the conductor tracks of the first conductor track plane intersecting the conductor tracks of the adjacent conductor track plane at intersecting regions and defining memory cells, and electrical contacts formed at selected memory cells between said conductor tracks of said first conductor track plane and of said at least one adjacent conductor track plane for representing a given logic state in the selected memory cell, the method which comprises:

selecting a given memory cell of the read only memory;

applying a first voltage to one conductor track of the selected cell;

applying a second voltage to the other conductor track of the selected cell;

applying a third voltage to all remaining conductor tracks; and

setting the first voltage lower than the third voltage, and the third voltage lower than the second voltage.

12. The method according to claim 11, wherein the third voltage is 0V.

13. The method according to claim 11, wherein the first voltage is -2V, and the second voltage is +2V.