Method for high-speed programming of a nonvolatile semiconductor memory device
DCFirst Claim
1. A method for programming a nonvolatile memory device having a plurality of memory cells grouped in a plurality of blocks, for storing multi-valued data represented as multi-valued threshold voltages, said method comprising the step of detecting a plurality of program data to be programmed in said memory cells in one of said blocks, and further, upon detecting a first value to be programmed in a first group of said memory cells in said one of blocks and a second value to be programmed in a second group of said memory cells in said one of blocks, the steps of consecutively applying a first programming voltage, which corresponds to said first value, to said first group and said second group maintained at a first potential, and applying a second programming voltage, which corresponds to said second value, to said second group.
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Abstract
A flash EEPROM has a plurality of multi-valued memory cells grouped in a plurality blocks or pages for parallel programming. If the data values for parallel programming include data "10" for a first group, data "01" for a second group and data "00" for a third group of memory cells in a page, a first voltage corresponding to data "10" is applied to the first through third groups, a second voltage corresponding to data "01" is applied to the second and the third groups, and a third voltage corresponding to data "00" is applied to the third groups, thereby reducing the programming time length for the parallel programming.
147 Citations
5 Claims
- 1. A method for programming a nonvolatile memory device having a plurality of memory cells grouped in a plurality of blocks, for storing multi-valued data represented as multi-valued threshold voltages, said method comprising the step of detecting a plurality of program data to be programmed in said memory cells in one of said blocks, and further, upon detecting a first value to be programmed in a first group of said memory cells in said one of blocks and a second value to be programmed in a second group of said memory cells in said one of blocks, the steps of consecutively applying a first programming voltage, which corresponds to said first value, to said first group and said second group maintained at a first potential, and applying a second programming voltage, which corresponds to said second value, to said second group.
Specification