Method for high-speed programming of a nonvolatile semiconductor memory device

• US 5,943,260 A
• Filed: 02/20/1998
• Issued: 08/24/1999
• Est. Priority Date: 02/21/1997
• Status: Expired due to Term

• Current Assignee: Limestone Memory Systems LLC (Acacia Research Corporation)
• Original Assignee: NEC Corporation
• Inventors: Hirakawa, Tsuyoshi
• Primary Examiner(s): YOO, DO H
• Application Number:
  US09/027,215
• Time in Patent Office: 550 Days
• Field of Search: 365/185.03, 365/185.11, 365/230.03, 365/185.19
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A flash EEPROM has a plurality of multi-valued memory cells grouped in a plurality blocks or pages for parallel programming. If the data values for parallel programming include data "10" for a first group, data "01" for a second group and data "00" for a third group of memory cells in a page, a first voltage corresponding to data "10" is applied to the first through third groups, a second voltage corresponding to data "01" is applied to the second and the third groups, and a third voltage corresponding to data "00" is applied to the third groups, thereby reducing the programming time length for the parallel programming.

Claims

1. A method for programming a nonvolatile memory device having a plurality of memory cells grouped in a plurality of blocks, for storing multi-valued data represented as multi-valued threshold voltages, said method comprising the step of detecting a plurality of program data to be programmed in said memory cells in one of said blocks, and further, upon detecting a first value to be programmed in a first group of said memory cells in said one of blocks and a second value to be programmed in a second group of said memory cells in said one of blocks, the steps of consecutively applying a first programming voltage, which corresponds to said first value, to said first group and said second group maintained at a first potential, and applying a second programming voltage, which corresponds to said second value, to said second group.

2. A method as defined in claim 1, wherein said second programming voltage with respect to said first potential is larger than said first programming voltage with respect to said first potential.

3. A method as defined in claim 1 wherein, upon detecting a third value to be programmed in a third group of said memory cells in said one of blocks in addition to said first and second groups, first and second programming voltage applying steps apply said first programming voltage and said second programming voltage to said third group, and said method comprises the step of applying a third programming voltage, which corresponds to said third value, to said third group.

4. A method as defined in claim 3, wherein said third programming voltage with respect to said first potential is larger than said second programming voltage with respect to said first potential.

5. A method as defined in claim 1, wherein said first and second programming voltages are applied to control gates of said first and second groups of memory cells through a corresponding word line, and select pulses are applied to drains of said first and second groups of memory cells through corresponding bit lines at timings of said first and second programming voltages.