Semiconductor power device

• US 5,945,730 A
• Filed: 02/05/1998
• Issued: 08/31/1999
• Est. Priority Date: 02/12/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Machuga, Steve Charles, Monroe, Conrad, Sicard, Thierry
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): DUONG, HUNG V
• Application Number:
  US09/019,292
• Time in Patent Office: 572 Days
• Field of Search: 257/341, 257/342, 257/666, 257/691, 257/207
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/14133 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]

Abstract

A semiconductor power device comprises a metal conductor (6) coupled to a semiconductor region (30) of the device, one or more bumps (8) formed in contact with the metal conductor (6) and a frame (14) formed of high conductivity material. The frame (14) comprises a connecting portion (18) for connecting to at least one of the one or more bumps (8) so as to provide an external connection to the semiconductor region (30) of the device.

Claims

1. A semiconductor power device comprising:

first and second semiconductor regions,

a plurality of first metal conductors coupled to the first semiconductor region, each of the plurality of first metal conductors having at least one bump in contact therewith,

a plurality of second metal conductors coupled to the second semiconductor region, each of the plurality of second metal conductors having at least one bump in contact therewith, and

a frame formed of high conductivity material, the frame comprising a plurality of first connection portions for connecting to the at least one bumps of the first metal conductors and a plurality of second connection portions for connecting to the at least one bumps of the second metal conductors, the frame providing external connections to the semiconductor regions of the device.

2. A semiconductor power device according to claim 1 wherein the plurality of first metal conductors are interdigitated with the plurality of second metal conductors.

3. A semiconductor power device according to claim 1 wherein each of the plurality of first and second metal conductors are arranged in parallel extending in a first direction.

4. A semiconductor power device according to claim 1 wherein each of the plurality of first metal conductors have a plurality of bumps in contact therewith and wherein each of the plurality of second metal conductors have a plurality of bumps in contact therewith.

5. A semiconductor power device according to claim 1 wherein each of the plurality of first and second metal conductors are arranged in parallel extending in a first direction and wherein each of the plurality of first and second metal conductors have a plurality of bumps arranged along the respective metal conductor in the first direction, such that the bumps on the first metal conductors are substantially aligned in first lines which extend in a second direction and such that the bumps on the second metal conductors are substantially aligned in second lines which extend in the second direction.

6. A semiconductor power device according to claim 5 wherein the second direction is substantially perpendicular to the first direction.

7. A semiconductor power device according to claim 5 wherein the second direction is skewed to the first direction.

8. A semiconductor power device according to claim 5 wherein the second lines alternate with the first lines.

9. A semiconductor power device according to claim 5 wherein the frame has a plurality of first connection portions, each of the first connection portions for connecting to the bumps arranged in a respective one of the first lines extending in the second direction and each of the second connection portions for connecting to the bumps arranged in a respective one of the second lines extending in the second direction.

10. A semiconductor lateral power transistor device comprising:

drain and source semiconductor regions;

a plurality of drain metal conductors coupled to the drain semiconductor region and extending in a first direction, each of the plurality of drain metal conductors having a plurality of the bumps in contact therewith and arranged along the respective drain metal conductor in the first direction, such that the bumps on the drain metal conductors are substantially aligned in first lines which extend in a second direction;

a plurality of source metal conductors coupled to the source semiconductor region and extending in parallel with the plurality of drain metal conductors in the first direction, each of the plurality of source metal conductors having a plurality of the bumps in contact therewith and arranged along the respective source metal conductor in the first direction, such that the bumps on the source metal conductors are substantially aligned in second lines which extend in the second direction; and

a frame formed of high conductivity material, the frame comprising a plurality of first and second connection portions, each of the first connection portions for connecting to the bumps arranged in a respective one of the first lines extending in the second direction and each of the second connection portions for connecting to the bumps arranged in a respective one of the second lines extending in the second direction, wherein the first and second connecting portions provide external connections to the drain and source semiconductor regions of the device.

11. A semiconductor lateral power transistor device according to claim 10 wherein the second direction is substantially perpendicular to the first direction.

12. A semiconductor lateral power transistor device according to claim 10 wherein the second direction is skewed to the first direction.