Method and apparatus for executing multiple transactions within a single arbitration cycle

• US 5,948,094 A
• Filed: 09/17/1997
• Issued: 09/07/1999
• Est. Priority Date: 09/29/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Solomon, Gary A., MacWilliams, Peter D., Rasmussen, Norman J.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/932,745
• Time in Patent Office: 720 Days
• Field of Search: 395/297, 395/293, 395/296, 395/298, 395/728, 395/729
• US Class Current: 710/118
• CPC Class Codes: G06F 13/3625 using a time dependent access

Abstract

A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.

Claims

1. An arbitration method comprising the steps of:

initiating a first arbitration event;

granting a first request for ownership of a first bus from a first bus agent coupled to the first bus for executing a first transaction;

starting a timer when the first request is granted;

executing the first transaction;

determining if the first bus agent is requesting continued ownership of the bus;

initiating a second arbitration event if it is determined that the first bus agent is not requesting continued ownership of the first bus;

if the first bus agent is requesting continued ownership of the bus,

determining if the timer has expired; and

granting a second request from the first bus agent for executing a second transaction before initiating the second arbitration event if the timer has not expired and initiating the second arbitration event if the timer has expired.

2. The arbitration method of claim 1, further comprising the steps of executing the second transaction and granting a third request from the first bus agent for executing a third transaction before initiating a second arbitration event if the timer has not expired.

3. The arbitration method of claim 1, wherein the timer is programmable by a user and applies to all REQ#/GNT# pairs.

4. The arbitration method of claim 1, wherein the timer is programmable by a user and applies to a single REQ#/GNT# pair, and a plurality of other timers, each of which being programmable by a user, applies to a plurality of other REQ#/GNT# pairs.

5. The arbitration method of claim 1, wherein the timer is hardwired with a fixed value and applies to all REQ#/GNT# pairs.

6. The arbitration method of claim 1, wherein the timer is hardwired with a fixed value and applies to a single REQ#/GNT# pair, and a plurality of other timers, each of which being hardwired with a fixed value, applies to a plurality of other REQ#/GNT# pairs.

7. The arbitration method of claim 1, wherein the first bus agent is a fragmented access bus agent and the first bus is a peripheral component interconnect (PCI) bus.

8. The arbitration method of claim 1, wherein the timer is started within a preset number of clock cycles of granting the first request.

9. The arbitration method of claim 1, wherein the first bus is a peripheral component interconnect (PCI) bus and the second request is granted by re-asserting GNT# for the first bus agent one clock cycle after the first bus agent de-asserts FRAME# if REQ# remains asserted by the first bus agent.

10. The arbitration method of claim 1, wherein the first bus is a peripheral component interconnect (PCI) bus and the second request is granted by maintaining an assertion of GNT# if REQ# remains asserted by the first bus agent.

11. The arbitration method of claim 7, wherein the fragmented access bus agent comprises a first buffer containing data which is written into a first set of consecutive address locations in a system memory during the first transaction, and a second buffer containing data which is written into a second set of consecutive address locations in the system memory during the second transaction, the first and second sets of consecutive address locations being located in separate regions of the system memory.

12. The arbitration method of claim 7, wherein the fragmented access bus agent is a bridge coupling the first bus to a second bus, a second bus agent and a third bus agent being coupled to the second bus, the second bus agent communicating with a target device during the first transaction, and the third bus agent communicating with the target device during the second transaction.

13. The arbitration method of claim 12, wherein the target device is coupled to the first bus.

14. The arbitration method of claim 12, wherein the target device is system memory.

15. An arbitration method, comprising the steps of:

initiating a first arbitration event;

granting a first request for ownership of a PCI bus from a fragmented access bus agent coupled to the PCI bus for executing a first transaction;

starting a timer when the first request is granted;

executing the first transaction;

determining if the bus agent is requesting continued ownership of the PCI bus;

initiating a second arbitration event if it is determined that the bus agent is not requesting continued ownership of the PCI bus;

determining if the timer has expired;

granting a second request from the bus agent for executing a second transaction before initiating the second arbitration event if the timer has not expired;

executing the second transaction;

determining if the bus agent is requesting continued ownership of the PCI bus;

initiating a second arbitration event if it is determined that the fragmented access bus agent is not requesting continued ownership of the PCI bus;

determining if the timer has expired;

granting a third request from the bus agent for executing a third transaction before initiating the second arbitration event if the timer has not expired; and

executing the third transaction before initiating the second arbitration event.

16. The arbitration method of claim 15, wherein the timer is programmable by a user.

17. The arbitration method of claim 15, wherein the timer is hardwired with a fixed value.

18. The arbitration method of claim 15, wherein the timer is started within approximately three clock cycles of granting the first request.

19. The arbitration method of claim 15, wherein the second request is granted by continuing an assertion of GNT# for the bus agent while REQ# remains asserted by the bus agent.

20. The arbitration method of claim 15, wherein the fragmented access bus agent is a video capture device comprising a first buffer containing data which is written into a first set of consecutive address locations in a system memory during the first transaction, a second buffer containing data which is written into a second set of consecutive address locations in the system memory during the second transaction, and a third buffer containing data which is written into a third set of consecutive address locations in the system memory during the third transaction, the first, second, and third sets of consecutive address locations being located in separate regions of the system memory.

21. A computer system, comprising:

a bus;

a bus agent coupled to the bus;

a bus arbiter coupled to the bus; and

a timer coupled to the bus arbiter, the timer starting when a first arbitration request for a first transaction is granted;

the bus arbiter permitting the bus agent to execute multiple transactions within a single arbitration cycle by granting the bus agent ownership of the bus to execute the first transaction, granting the bus agent ownership of the bus to execute a second transaction if the bus agent continues to assert a request for ownership of the bus and the timer has not expired.

22. The computer system of claim 21, wherein the bus is a peripheral component interconnect (PCI) bus and the arbiter and the timer are contained within a bridge coupling the PCI bus to a processor and system memory.

23. The computer system of claim 21, wherein the timer is programmable by a user and is started within approximately three clock cycles of granting the bus agent ownership of the bus for executing a first transaction within the single arbitration cycle.

24. The computer system of claim 21, wherein the timer is hardwired with a fixed value and is started within approximately three clock cycles of granting the bus agent ownership of the bus for executing a first transaction within the single arbitration cycle.

25. The computer system of claim 22, wherein the bus agent comprises a first buffer containing data which is written into a first set of consecutive address locations in the system memory during a first transaction, and a second buffer containing data which is written into a second set of consecutive address locations in the system memory during a second transaction, the first and second sets of consecutive address locations being located in separate regions of the system memory, and the first and second transactions being executed within the single arbitration cycle.