Synchronous memory device having a programmable register and method of controlling same

  • US 5,953,263 A
  • Filed: 11/20/1998
  • Issued: 09/14/1999
  • Est. Priority Date: 02/10/1997
  • Status: Expired due to Fees
First Claim
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1. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

  • a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request.

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