Synchronous memory device having a programmable register and method of controlling same

• US 5,953,263 A
• Filed: 11/20/1998
• Issued: 09/14/1999
• Est. Priority Date: 02/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/196,200
• Time in Patent Office: 298 Days
• Field of Search: 395/194, 395/189.12, 395/230.03, 395/240, 395/290, 395/292, 395/297, 395/298, 395/309, 395/310, 395/828, 395/856
• US Class Current: 365/194
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request.

2. The synchronous memory device of claim 1 further including output drivers, coupled to an external bus, to output data on the bus, in response to the read request, synchronously with respect to an external clock.

3. The synchronous memory device of claim 2 wherein the value is representative of a number of clock cycles of the external clock.

4. The synchronous memory device of claim 1 wherein, during an initialization sequence, the programmable register stores the value.

5. The synchronous semiconductor memory device of claim 1 wherein, in response to a control register access, the programmable register stores the value.

6. The synchronous semiconductor memory device of claim 5 wherein the control register access and the value which is representative of a delay time are provided to the memory device in a single request packet.

7. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprising:

a programmable register to store a value which is representative of a programmable delay time after which the memory device responds to a transaction request; and

wherein the memory device responds to a first transaction request in accordance with a fixed delay time and, after programming the programmable register, responds to the second transaction request in accordance with the programmable delay time.

8. The synchronous semiconductor memory device of claim 7 further including a pre-programmed register to store a value which is representative of the fixed delay time.

9. The synchronous semiconductor memory device of claim 7 wherein the value which is representative of the programmable delay time is stored in the programmable register after power is applied to the synchronous memory device.

10. The synchronous semiconductor memory device of claim 7 wherein the value which is representative of the programmable delay time is stored in the programmable register after the memory device is reset.

11. The synchronous semiconductor memory device of claim 7 wherein, during an initialization sequence, the programmable register stores the value.

12. The synchronous semiconductor memory device of claim 7 wherein, in response to a control register access, the value which is representative of the programmable delay time is stored in the programmable register.

13. The synchronous semiconductor memory device of claim 12 wherein the control register access and the value which is representative of the programmable delay time are provided to the memory device in a single request packet.

14. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprising:

a programmable register to store a value which is representative of a number of clock cycles of an external clock to transpire before data is output onto an external bus in response to a read request; and

a plurality of output drivers, coupled to the bus, to output data in response to the read request, wherein the output drivers output data on the bus after the number of clock cycles of the external clock transpire.

15. The synchronous memory device of claim 14 wherein the value is representative of a fraction or a whole number of clock cycles of the external clock.

16. The synchronous memory device of claim 14 wherein, during an initialization sequence, the programmable register stores the value.

17. The synchronous semiconductor memory device of claim 14 wherein, in response to a control register access, the programmable register stores the value.

18. A method of controlling the operation of a synchronous semiconductor memory device wherein the memory device includes a register, the method comprising:

providing a time delay value to the memory device;

storing the time delay value in the register in the memory device, wherein the time delay value is representative of a time delay after which the memory device responds to a transaction request.

19. The method of claim 18 further including issuing a control register access wherein, in response to the control register access, the memory device stores a time delay value in the register.

20. The method of claim 18 wherein the control register access and the time delay value are provided to the memory device in a single request packet.

21. The method of claim 18 further including initializing the register by providing a time delay value to the memory device after issuing a control register access.

22. The method of claim 21 wherein the control register access and the time delay value are provided to the memory device in a single request packet.

23. The method of claim 18 further including initializing the register after the memory device is powered-up or reset.

24. The method of claim 18 further including selecting one of a plurality of time delays after which the memory device is to provide data in response to a read request.

25. The method of claim 18 wherein the transaction request is a read request.

26. The method of claim 19 wherein the transaction request is a write request.

27. A method of operation of a semiconductor memory device wherein the memory device includes a programmable register, the method comprising:

receiving a time delay value, wherein the time delay value is representative of a number of clock cycles of an external clock to transpire before data is output onto an external bus in response to a read request; and

storing the time delay value in the register.

28. The method of claim 27 further including receiving a control register access wherein, in response to the the register stores the time delay value.

29. The method of claim 28 further including receiving the control register access and the time delay value in one request packet.

30. An integrated circuit device having memory including at least one memory section which includes a plurality of memory cells, the integrated circuit device comprising:

a programmable register to store a value which is representative of a number of clock cycles of a clock to transpire before data is output onto a bus in response to a read request; and

a plurality of output drivers, coupled to the bus, to output data in response to the read request, wherein the output drivers output data on the bus after the number of clock cycles of the clock transpire and synchronously with respect to the clock.

31. The integrated circuit device of claim 30 wherein the value is representative of a fraction or a whole number of clock cycles of the clock.

32. The integrated circuit device of claim 30 wherein, during an initialization sequence, the programmable register stores the value.

33. The integrated circuit device of claim 30 wherein the integrated circuit device stores the value in the register in response to a control register access.