DRAM incorporating self refresh control circuit and system LSI including the DRAM

  • US 5,959,925 A
  • Filed: 11/03/1998
  • Issued: 09/28/1999
  • Est. Priority Date: 06/01/1998
  • Status: Expired due to Term
First Claim
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1. A dynamic random access memory incorporating a self refresh control circuit comprising:

  • a memory cell array comprising a plurality of memory cells; and

    a self refresh address control section for setting a period of a self refresh operation for said memory cell array having said plurality of memory cells and for providing an address signal to said memory cell array in order to perform said self refresh operation for said memory cell array, and said self refresh address control section comprising;

    a self refresh control circuit for inputting a control signal to optionally set a period of the self refresh operation and for setting a period of an address signal of the self refresh operation based on the received control signal, and for outputting a self cycle signal of the period that has been set; and

    a row address buffer for inputting the self cycle signal that has been set by said self refresh control circuit, and for outputting the address signal to said memory cell array based on the self cycle signal as a trigger signal.

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