DRAM incorporating self refresh control circuit and system LSI including the DRAM

• US 5,959,925 A
• Filed: 11/03/1998
• Issued: 09/28/1999
• Est. Priority Date: 06/01/1998
• Status: Expired due to Term

• Current Assignee: Vachellia LLC (Acacia Research Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tatsumi, Takashi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/184,646
• Time in Patent Office: 329 Days
• Field of Search: 365/222, 365/189.05, 365/230.06, 365/230.08, 365/236
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A DRAM and a system LSI incorporating the DRAM. The DRAM has a self refresh address control section (11) inputs a control signal to optionally specify a period of a self refresh operation for the DRAM, a self refresh control circuit (7,71) for specifying the period of an address signal to be used for the self refresh operation and for outputting a self cycle signal, and a row address buffer (8) for providing addresses to the memory cell array (10) based on the self cycle signal as a trigger signal.

Claims

1. A dynamic random access memory incorporating a self refresh control circuit comprising:

a memory cell array comprising a plurality of memory cells; and

a self refresh address control section for setting a period of a self refresh operation for said memory cell array having said plurality of memory cells and for providing an address signal to said memory cell array in order to perform said self refresh operation for said memory cell array, and said self refresh address control section comprising;

a self refresh control circuit for inputting a control signal to optionally set a period of the self refresh operation and for setting a period of an address signal of the self refresh operation based on the received control signal, and for outputting a self cycle signal of the period that has been set; and

a row address buffer for inputting the self cycle signal that has been set by said self refresh control circuit, and for outputting the address signal to said memory cell array based on the self cycle signal as a trigger signal.

2. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 1, wherein said self refresh control circuit comprises:

a refresh control register; and

a self refresh period counter, wherein said self refresh control register inputs a control signal to optionally specify a period of the self refresh operation for said memory cell array, outputs a magnification control signal indicating the period of the address signal for the self refresh operation based on the control signal to optionally specify the period of the self refresh operation, and wherein said self refresh period counter inputs the magnification control signal, generates a self cycle signal, and outputs the generated self cycle signal to said row address buffer.

3. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 1, wherein said self refresh control circuit comprises:

a decoder and a self refresh period counter, wherein said decoder inputs a control signal to optionally specify a period of the self refresh operation, decoding the control signal in order to generate and output a magnification control signal indicating the period of the self refresh operation based on the control signal to optionally specify the period of the self refresh operation, and wherein said self refresh period counter inputs the magnification control signal, generates a self cycle signal, and outputs the generated self cycle signal to said row address buffer.

4. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 1, further comprising a self cycle control pin in order to provide the self cycle signal, to be transferred from said self refresh control circuit to said row address buffer, into external devices, and wherein said self cycle signal is transferred to said external devices through said self cycle control pin to control the period of the self refresh operation.

5. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 2, further comprising a self cycle control pin in order to provide the self cycle signal, to be transferred from said self refresh control circuit to said row address buffer, into external devices, and wherein said self cycle signal is transferred to said external devices through said self cycle control pin to control the period of the self refresh operation.

6. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 3, further comprising a self cycle control pin in order to provide the self cycle signal, to be transferred from said self refresh control circuit to said row address buffer, into external devices, and wherein said self cycle signal is transferred to said external devices through said self cycle control pin to control the period of the self refresh operation.

7. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 1, further comprising a read/write control circuit for transferring an enable signal to a column decoder and a data output buffer during the self refresh operation in order to operate said column decoder and said data output buffer, and wherein data items stored in said memory cell array are transferred to external devices based on the period of the self refresh operation that has been set by said self refresh control circuit.

8. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 2, further comprising a read/write control circuit for transferring an enable signal to a column decoder and a data output buffer during the self refresh operation in order to operate said column decoder and said data output buffer, and wherein data items stored in said memory cell array are transferred to external devices based on the period of the self refresh operation that has been set by said self refresh control circuit.

9. A dynamic random access memory incorporating a self refresh control circuit as claimed in claim 3, further comprising a read/write control circuit for transferring an enable signal to a column decoder and a data output buffer during the self refresh operation in order to operate said column decoder and said data output buffer, and wherein data items stored in said memory cell array are transferred to external devices based on the period of the self refresh operation that has been set by said self refresh control circuit.

10. A system LSI comprising:

said dynamic random access memory as claimed in claim 1; and

a system for inputting data items from said DRAM and outputting data items to said DRAM, and processing the data items.

11. A system LSI comprising:

said dynamic random access memory as claimed in claim 2; and

a system for inputting data items from said DRAM and outputting data items to said DRAM, and processing the data items.

12. A system LSI comprising:

said dynamic random access memory as claimed in claim 3; and

a system for inputting data items from said DRAM and outputting data items to said DRAM, and processing the data items.

13. A system LSI comprising:

said dynamic random access memory as claimed in claim 4; and

a system for inputting data items from said DRAM and outputting data items to said DRAM, and processing the data items.

14. A system LSI comprising:

said dynamic random access memory as claimed in claim 7; and

a system for inputting data items from said DRAM and outputting data items to said DRAM, and processing the data items.