Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement

• US 5,962,926 A
• Filed: 09/30/1997
• Issued: 10/05/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sharma, Laxminarayan, Torres, Victor Manuel, Srikantappa, Ashok
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US08/940,605
• Time in Patent Office: 735 Days
• Field of Search: 257/786, 257/737, 257/738, 257/784
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]

Abstract

The present invention comprises a semiconductor device (20) having a active circuit (22) and a bond pad area (24). Within the bond pad area there are a plurality of rows of bond pads. Sets of bond pads (30-36) include one bond pad from each row. The bond pads (26) are uniquely positioned within the bond pad area (24) to allow for a first wire pitch between pads which are adjacent and in the same set, and a second wire pitch between pads which are adjacent and in different sets. A method of determining placement of the bond pads (26) is taught.

Claims

1. A semiconductor device comprising:

a die having four sides;

a first side of the die having;

a first row of bond pads positioned substantially along a first axis offset from and parallel to the first side of the die by a first distance;

a second row of bond pads positioned substantially along a second axis offset from and parallel to the first side of the die by a second distance which is greater than the first distance;

wherein

each bond pad of the first row has a first and a second side substantially perpendicular to the first side of the die.

each bond pad of the second row has a first and a second side substantially perpendicular to the first side of the die, the first side of each bond pad of the second row forming a pad placement axes,

each pad placement axes intersecting a corresponding bond pad associated with the first row of bond pads where the pad placement axes is not coincident with the first or second side of the corresponding bond pad.

2. The semiconductor device of claim 1 further comprising:

a plurality of conductive interconnects, each of the conductive interconnects electrically contacting a predetermined one of the bond pads of the first and second rows and extending from the side of the die external to the die for electrical contact to the circuitry, the plurality of conductive interconnects being positioned in substantially the same plane.

3. The semiconductor device of claim 1 wherein the four sides of the die form eight sections and within each of the eight sections there is a pitch between each bond pad in each row, the pitch being a distance between centers of adjacent bond pads, wherein for each row the pitch varies within a single section from a beginning bond pad of the section to a last bond pad of the section.

4. The semiconductor device of claim 3 wherein at least a portion of the of the plurality of wires extend from the side of the die at an angle other than substantially orthogonal to the side of the die.

5. The semiconductor device of claim 2 wherein the plurality of conductive interconnects is a plurality of wires which form wire bonds looped between the bond pads and a plurality of bond posts which are offset from the side of the die, each wire which is looped between a predetermined bond pad and a predetermined bond post having a substantially same loop height referenced from the plane containing the conductive interconnects.

6. The semiconductor device of claim 2 wherein the plurality of conductive interconnects is a plurality of wires which form wire bonds between the bond pads and a plurality of bond posts which are positioned along the side of the die, and wherein the adjacent wire bonds of the first and second rows which are coincident with each other form sets of wire bonds, each wire bond set having a first wire pitch defining distance between wires in the wire bond set, and adjacent wires between sets having a second wire pitch, the first wire pitch being less than the second wire pitch along all of the side of the die.

7. The semiconductor device of claim 1 further comprising a third row of bond pads for each section of the device to form sets of bond pads containing a bond pad from each row, wherein within each set a third row bond pad is positioned more toward a center of the section than a second row bond pad, and a second row bond pad is positioned more toward the center of the section than the first row bond pad.

8. The semiconductor device of claim 6 wherein in each section a beginning bond pad of the section is located at substantially a center line of one of the four sides of the die and the last bond pad of the section is located at substantially a corner of the die, the pitch between each bond pad sequentially increasing from the center line to the corner within the first row of bond pads.

9. The semiconductor device of claim 3 wherein in each section pitch variation between each bond pad of the first row differs from pitch variation of the second row.

10. The semiconductor device of claim 3 further comprising a third row of bond pads for each section of the device, each bond pad of the third row being associated with a corresponding bond pad of each of the first and second rows, wherein a pitch between centers of associated bond pads of the first, second and third rows is substantially the same.

11. A semiconductor device comprising:

a die having a plurality of bond pads located around an outer perimeter, the bond pads being placed in at least first, second and third parallel rows displaced from the outer perimeter such that the third row is farther from the outer perimeter than the second row which is farther than first row from the outer perimeter, the bond pads forming a sets of bond pads having a bond pad from the first, second and third rows, within each set a bond pad of the third row is positioned closer to a center of the section of bond pads than a bond pad of the second row of the set, and the bond pad of the second row is closer to the center of the section of bond pads than a bond pad of the first row.

12. The semiconductor device of claim 11 further comprising:

a plurality of conductive interconnects which make electrical connection to selective ones of the bond pads of the first, second and third rows, all the conductive interconnects being substantially in a same plane.

13. The semiconductor device of claim 11 further comprising:

a plurality of wire bonds which make electrical connection to selective ones of the bond pads of the first, second and third rows, wires of the wire bonds associated with each set of bond pads having a first pitch which is the same within each set but which may vary from set to set, and wires adjoining each set having a second pitch which may vary from set to set boundaries, the second pitch always being greater than the first pitch within any section of bond pads.

14. The semiconductor device of claim 11 wherein within each of the sections of bond pads there is a pitch between each bond pad in each of the first, second and third rows, the pitch being a distance between centers of adjacent bond pads, wherein for each row the pitch varies within a same section from a beginning bond pad of the section to a last bond pad of the same section.

15. A semiconductor device comprising:

a die having a first edge and a second edge, wherein the first edge is substantially orthogonal to the second edge;

a first row of bond pads positioned along a first axis substantially parallel with the first edge of a semiconductor die, the first row including a first pad and a second pad;

a second row of bond pads, including a third pad and a fourth pad, positioned along a second axis substantially parallel with the first edge of a semiconductor die, where the second axis is located further from the edge that the first axis, the first row including a third pad and a fourth pad;

wherein each of the first, second, third, and fourth bond pads have a first and second edge substantially parallel to the second edge of the die, and the first edge of each of the first, second, third, and fourth bond pads is closer to the second edge of the die than the respective bond pad'"'"'s second edge;

wherein an axis coincident to the second edge of the first bond pad intersects the third bond pad while an axis coincident to the first edge of the first bond pad does not intersect the third bond pad, and an axis coincident to the first edge of the second bond pad intersects the fourth bond pad while an axis coincident to the first edge of the first bond pad does not intersect the fourth bond pad.

16. A semiconductor device comprising:

a die having a first edge;

a first and a second bond pad associated with the first edge,

the first bond pad between the second bond pad and the edge, and having a first and second edge perpendicular to the first edge of the die, wherein

only one of an axis coincident with the first edge of the first bond pad and an axis coincident the second edge of the first bond pad intersects the second bond pad.