Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device

• US 5,963,476 A
• Filed: 11/12/1997
• Issued: 10/05/1999
• Est. Priority Date: 09/05/1996
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Shiau, Tzeng-Huei, Lee, I-Long, Hung, Chun Hsiung, Wan, Ray-Lin, Shone, Fuchia, Cheng, Yao-Wu
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/975,516
• Time in Patent Office: 692 Days
• Field of Search: 365/185.29, 365/218, 365/185.18, 365/185.22, 365/185.28
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

Claims

1. A method for pre-programming a block of floating gate memory cells in preparation for erasing the block, the memory cells in the block being formed in a channel well within an isolation well in a semiconductor substrate and having floating gates, sources, drain and control gates, comprising:

setting word lines coupled to the control gates of memory cells in the block to a pre-program word line potential;

applying a pre-program channel potential to the channel well of memory cells in the block to induce transfer of electrons to set charge levels in the floating gates of cells in the block so that charge levels in the floating gates of memory cells establish a pre-programmed state for the memory cells in the block; and

verifying the pre-programming of memory cells in the block.

2. The method of claim 1, wherein the block includes a plurality of rows and columns of cells in which rows of cells in the block are coupled with corresponding word lines, and columns of cells in the block are coupled with corresponding bit lines, and wherein the step of setting word lines to the pre-program word line potential includes setting word lines corresponding to the plurality of rows to the pre-program word line potential.

3. The method of claim 1, wherein the block includes a plurality of rows and a plurality of columns of cells in which rows of cells in the block are coupled with corresponding word lines, and columns of cells in the block are coupled with corresponding bit lines, and wherein the step of verifying the pre-programming includes:

applying a verify potential to word lines corresponding to the plurality of rows, and

sensing at least one bit line corresponding to a column of cells in the plurality of columns to verify that the memory cells in the column and in the plurality of rows are in the pre-programmed state.

4. The method of claim 1, wherein the block includes a plurality of rows and a plurality of columns of cells in which rows of cells in the block are coupled with corresponding word lines, and columns of cells in the block are coupled with corresponding bit lines, and wherein the step of verifying the pre-programming includes:

applying a verify potential to word lines corresponding to the plurality of rows, and

sensing a set of bit lines corresponding to at least eight columns of cells in the plurality of columns to verify that the memory cells in the at least eight columns and in the plurality of rows are in the pre-programmed state.

5. The method of claim 1, wherein the pre-program channel potential has a value in a range of about negative 4 to negative 8 volts.

6. The method of claim 5, wherein the pre-program word line potential has a value in a range of about positive 3 to positive 10 volts.

7. The method of claim 1, including:

if cells in the block do not pass the step of verifying, then retrying the steps of applying and verifying, until all cells pass the step of verifying or until a retry limit is reached.

8. The method of claim 1, wherein the step of verifying includes reading memory cells in the block byte by byte.

9. The method of claim 1, wherein there are a plurality of blocks of floating gate memory cells on the semiconductor substrate, and including before the step of setting, selecting a block to be pre-programmed.

10. The method of claim 9, wherein more than one block in the plurality of blocks share a channel well, and including prior to the step of applying, setting word lines corresponding to rows in an unselected block sharing a channel well with a selected block to a pre-program inhibit potential.

11. The method of claim 10, wherein the pre-program inhibit voltage has a value in a range of about negative 4 to negative 8 volts.

12. The method of claim 1 further includes applying a pre-program source potential to the sources of the memory cells in the block.

13. The method of claim 12, wherein the pre-program source potential has a value between about ground and -8V.

14. The method of claim 1 further including applying a pre-program drain potential to the drains of the memory cells in the block.

15. The method of claim 14, wherein the pre-program drain potential has a value between about ground and -8V.

16. A method for erasing a block of floating gate memory cells, including a plurality of rows and columns of cells, the memory cells in the block being formed in a channel well within an isolation well in a semiconductor substrate, and floating gate memory cells in the block including respective floating gates, control gates, sources, drains, and channels, the method comprising:

pre-programming the block of cells by biasing the cells in parallel to induce tunneling of electrons to establish a charge condition in the floating gates of cells in the block corresponding to a pre-programmed state in cells in the block; and

erasing the block of cells by biasing the cells in parallel to induce tunneling of electrons to establish a charge condition in the floating gates of the cells in the block, after the step of pre-programming, corresponding to an erased state in the cells in the block.

17. The method of claim 16, wherein the step of pre-programming includes establishing a pre-programming electric field between the channels and the floating gates of cells in the block, by applying a first pre-programming potential to the channel well and a second pre-programming potential to the control gates of cells in the block.

18. The method of claim 17, wherein the first pre-programming potential has a value within a range of about 0 volts to about negative 12 volts, and the second pre-programming potential has a value in the range of about 0 volts to about positive 12 volts.

19. The method of claim 16, wherein the step of pre-programming includes establishing a pre-programming electric field between the sources and the floating gates of cells in the block, by applying a first pre-programming potential to the sources of cells in the block and a second pre-programming potential to the control gates of cells in the block.

20. The method of claim 19, wherein the first pre-programming potential has a value within a range of about 0 volts to about negative 12 volts, and the second pre-programming potential has a value in the range of about 0 volts to about positive 12 volts, with the drains floating, and including applying a third pre-programming potential to the channel well having a value within a range of about 0 volts to about negative 12 volts.

21. The method of claim 16, wherein the step of pre-programming includes establishing a pre-programming electric field between the drains and the floating gates of cells in the block, by applying a first pre-programming potential to the drains of cells in the block and a second pre-programming potential to the control gates of cells in the block.

22. The method of claim 21, wherein the first pre-programming potential has a value within a range of about 0 volts to about negative 12 volts, and the second pre-programming potential has a value in the range of about 0 volts to about positive 12 volts, with the sources floating, and including applying a third pre-programming potential to the channel well having a value within a range of about 0 volts to about negative 12 volts.

23. The method of claim 16, wherein the block includes a plurality of rows and a plurality of columns of cells in which control gates of cells along rows in the block are coupled with corresponding word lines, and drains of cells along columns in the block are coupled with corresponding bit lines, and the step of pre-programming comprises:

setting word lines of memory cells in the block to a pre-program word line potential;

applying a pre-program channel potential to the channel well of memory cells in the block to induce tunneling of electrons between the floating gates of cells in the block and the channel well so that charge levels in the floating gates of memory cells establish a pre-programmed state for the memory cells in the block; and

verifying the pre-programming of memory cells in the block.

24. The method of claim 23, wherein the step of verifying the pre-programming includes:

applying a verify potential to word lines corresponding to the plurality of rows, and

sensing at least one bit line corresponding to a column of cells in the plurality of columns to verify that the memory cells in the column and in the plurality of rows are in the pre-programmed state.

25. The method of claim 23, wherein the step of verifying the pre-programming includes:

applying a verify potential to word lines corresponding to the plurality of rows, and

sensing a set of bit lines corresponding to at least eight columns of cells in the plurality of columns to verify that the memory cells in the at least eight columns and in the plurality of rows are in the pre-programmed state.

26. The method of claim 23, wherein the pre-program channel potential has a value in a range of about negative 4 to negative 8 volts.

27. The method of claim 26, wherein the pre-program word line potential has a value in a range of about positive 3 to positive 10 volts.

28. The method of claim 23, including:

if cells in the block do not pass the step of verifying, then retrying the steps of applying and verifying, until all cells pass the step of verifying or until a retry limit is reached.

29. The method of claim 23, wherein the step of verifying includes reading memory cells in the block byte by byte.

30. The method of claim 16, wherein there are a plurality of blocks of floating gate memory cells on the semiconductor substrate, and including before the step of pre-programming, selecting a block to be erased.

31. The method of claim 17, wherein there are a plurality of blocks of floating gate memory cells on the semiconductor substrate, and more than one block in the plurality of blocks share a channel well, and including prior to the step of pre-programming:

selecting one or more blocks to be erased; and

setting control gates of cells in an unselected block sharing a channel well with a selected block to a pre-program inhibit potential.

32. The method of claim 31, wherein the pre-program inhibit voltage has a value in a range of about 0 volts to about negative 12 volts.

33. A method for erasing selected blocks of floating gate memory cells in an array including a plurality of blocks, the memory cells in the plurality of blocks being formed in a corresponding channel well within an isolation well in a semiconductor substrate, and wherein the blocks in the plurality of blocks include a plurality of rows and columns of cells in which rows of cells in the block are coupled with corresponding word lines, and columns of cells in the block are coupled with corresponding bit lines, comprising:

selecting one or more blocks in the plurality of blocks to be erased;

setting word lines of memory cells in the selected one or more blocks to a pre-program word line potential having a positive value;

applying a pre-program channel potential having a negative value to the channel well of memory cells in the selected one or more blocks to induce transfer of electrons into the floating gates of cells in the selected one or more blocks from the channel well so that charge levels in the floating gates of memory cells establish a pre-programmed state for the memory cells in the selected one or more blocks;

removing the pre-programming word line potential from the word lines and removing the pre-program channel potential from the channel well of the selected one or more blocks, and applying a verify potential to word lines corresponding to the plurality of rows in the selected one or more blocks;

verifying the pre-programming of the selected one or more blocks by sensing at least one bit line at a time corresponding to a column of cells in the plurality of columns to verify that the memory cells in the column and in the plurality of rows in the selected one or more blocks are in the pre-programmed state;

if cells in the selected one or more blocks do not pass the step of verifying, then retrying the steps of setting, applying, removing and verifying for blocks which do not pass, until all cells in the selected one or more blocks pass the step of verifying or until a retry limit is reached; and

if all cells in the selected one or more blocks pass the step of verifying, then erasing the one or more selected blocks of floating gate memory cells by inducing tunneling of electrons to the channels from the floating gates of the cells to establish an erased state in the cells in the selected one or more blocks.

34. The method of claim 33, wherein the pre-program channel potential has a value in a range of about negative 4 to negative 8 volts.

35. The method of claim 34, wherein the pre-program word line potential has a value in a range of about positive 3 to positive 10 volts.

36. The method of claim 33, wherein more than one block in the plurality of blocks share a channel well, and including prior to the step of applying, setting word lines corresponding to rows in an unselected block sharing a channel well with a selected block to a pre-program inhibit potential.

37. The method of claim 36, wherein the pre-program inhibit voltage has a value in a range of about negative 4 to negative 8 volts.

38. The method of claim 33, including before the step of removing, applying a pre-program source potential to sources of memory cells in the selected one or more blocks, while the drains float.

39. The method of claim 33, including before the step of removing, applying a pre-program drain potential to drains of memory cells in the selected one or more blocks, while the sources float.

40. A method for erasing a block of floating gate memory cells, the respective cells in the block including a drain, a source, a floating gate and a control gate, on a semiconductor substrate having a first conductivity type, the substrate including an isolation well having a second conductivity type different than the substrate, a channel well within the isolation well having the first conductivity type, and source and drain regions for the cells in the block having the second conductivity type within the channel well, the method comprising:

pre-programming cells in the block by inducing tunneling current between the floating gates and the channel well to pre-program cells in the block by applying respective pre-programming potentials to the control gates, to the channel well, to the isolation well and to the substrate, the pre-programming potentials applied to the control gates and the channel well set to establish an electric field between the control gates and the channel well sufficient to induce tunneling current of electrons into the floating gates, the pre-programming potential applied to the isolation well set so that current between the channel well and the isolation well is blocked, and the pre-programming potential applied to the substrate set so that current between the isolation well and substrate is blocked; and

erasing the cells in the block by inducing tunneling current between the floating gates and the channel well to erase the pre-programmed cells in the block by applying respective erasing potentials to the control gates, to the channel well, to the isolation well and to the substrate, the erasing potentials applied to the control gates and the channel well set to establish an electric field between the control gates and the channel well sufficient to induce tunneling current of electrons out of the floating gates, the erasing potential applied to the isolation well set so that current between the channel well and the isolation well is blocked, and the erasing potential applied to the substrate set so that current between the isolation well and substrate is blocked.

41. The method of claim 40, wherein during the step of erasing, the erasing potential applied to the control gate is negative, and the erasing potential applied to the channel well is positive.

42. The method of claim 41, wherein the erasing potential applied to the isolation well is near the erasing potential applied to the channel well, and the fourth potential is less than the third potential.

43. The method of claim 41, wherein the substrate is coupled to an external reference supply applying a ground potential and a positive supply potential, and wherein erasing potential applied to the channel well is higher than the supply potential.

44. The method of claim 41, wherein the erasing potential applied to the isolation well is near the erasing potential applied to the channel well, and the fourth potential is near the ground potential.

45. The method of claim 41, wherein the supply potential is less than five volts.

46. The method of claim 40, wherein during the step of pre-programming, the pre-programming potential applied to the channel well is negative, and the pre-programming potential applied to the control gate is positive.

47. The method of claim 46, wherein the pre-programming potential applied to the isolation well is positive, and the pre-programming potential applied to the substrate is less than the pre-programming potential applied to the isolation well.

48. The method of claim 40, wherein the substrate is coupled to an external reference supply applying a ground potential and a positive supply potential, and wherein during the step of pre-programming, the pre-programming potential applied to the channel well is negative, and the pre-programming potential applied to the control gate is positive, the pre-programming potential applied to the isolation well is near the supply potential, and the pre-programming potential applied to the substrate is near ground.

49. The method of claim 40, including during the step of pre-programming, applying a potential to the sources of cells in the block, while the drains float.

50. The method of claim 40, including during the step of pre-programming, applying a potential to the drains of cells in the block, while the sources float.