Method of forming memory cell with built-in erasure feature

• US 5,963,806 A
• Filed: 08/19/1997
• Issued: 10/05/1999
• Est. Priority Date: 12/09/1996
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Sung, Kuo-Tung, Chu, Wen-Ting, Wu, Huoy-Jong
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US08/916,758
• Time in Patent Office: 777 Days
• Field of Search: 438/182, 438/257, 438/258, 438/259, 438/261, 438/263, 438/264, 438/266, 438/286, 438/374, 438/579, 438/588, 438/397, 438/555, 438/593, 438/305
• US Class Current: 438/266
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

A method of fabricating an E² PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

Claims

1. A process for fabricating a semiconductor memory device, comprising the steps of:

forming a plurality of insulation regions on a semiconductor substrate to define at least one active region on the substrate;

forming a first insulating layer on said active region;

forming a patterned first silicon layer on a portion of said first insulating layer;

forming a patterned second insulating layer overlying at least a portion of said first silicon layer;

forming a recess in said first insulating layer underneath said first silicon layer by removing portions of said first insulating layer between said first silicon layer and said substrate, said recess exposing portions of said substrate and said first silicon layer;

forming a patterned third insulating layer on said exposed portions of said substrate and said first silicon layer, said third insulating layer partially filling said recess; and

forming a patterned second silicon layer covering at least a portion of said third insulating layer and further filling said recess, wherein said second silicon layer includes at least one of a sharp tip and a wedge filling said recess.

2. The process as in claim 1, wherein said first insulating layer is silicon dioxide.

3. The process as in claim 1, wherein said first insulating layer is approximately 5 to 50 nm thick.

4. The process as in claim 1, wherein said first silicon layer is approximately 50 to 500 nm thick.

5. The process as in claim 1, wherein said first silicon layer is polycrystalline silicon.

6. The process as in claim 1, wherein said second insulating layer is silicon dioxide.

7. The process as in claim 6, wherein said silicon dioxide layer is approximately 5 to 200 nm thick.

8. The process as in claim 1, wherein said recess is formed by isotropic etching.

9. The process as in claim 1, wherein said second silicon layer is approximately 30 to 500 nm thick.

10. The process as in claim 1, further comprising the steps of:

forming a patterned fourth insulating layer on at least a portion of said second silicon layer; and

forming a patterned third silicon layer on at least a portion of said fourth insulating layer.

11. The process as in claim 10, wherein said first insulating layer is silicon dioxide.

12. The process as in claim 10, wherein said first insulating layer is approximately 5 to 50 nm thick.

13. The process as in claim 10, wherein said first silicon layer is approximately 50 to 500 nm thick.

14. The process as in claim 10, wherein said first silicon layer is polycrystalline silicon.

15. The process as in claim 10, wherein said second insulating layer is silicon dioxide.

16. The process as in claim 15, wherein said second insulating layer is approximately 10 to 200 nm thick.

17. The process as in claim 10, wherein said recess is formed by isotropic etching.