Metal plug local interconnect

• US 5,965,924 A
• Filed: 07/24/1997
• Issued: 10/12/1999
• Est. Priority Date: 11/22/1995
• Status: Expired due to Term

• Current Assignee: DSS Technology Management, Inc. (Document Security Systems, Inc.)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Yen, Ting P.
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US08/900,047
• Time in Patent Office: 810 Days
• Field of Search: 257/382, 257/383, 257/387, 257/388, 257/903, 437/190, 437/192, 438/647, 438/649
• US Class Current: 257/383
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Claims

1. A semiconductor structure comprising:

a silicon substrate having a top surface,

a diffusion region formed in said substrate adjacent to said top surface,

a gate formed on the top surface of said substrate juxtaposed to but not contacting said diffusion region,

a sidewall spacer adjacent to said gate and disposed above said diffusion region,

an insulator layer substantially covering said gate and said diffusion region, and

a conducting plug at least partially filling a via in said insulation layer that exposes said sidewall spacer in the absence of said conducting plug, said conducting plug providing direct electrical communication between said gate and said diffusion region.

2. A semiconductor structure according to claim 1, wherein said diffusion region is an N+ or a P+ region.

3. A semiconductor structure according to claim 1, wherein said insulator layer is formed of a material selected from the group consisting of silicon oxide and silicon nitride.

4. A semiconductor structure according to claim 1, wherein said electrically conducting plug is a metal plug.

5. A semiconductor structure according to claim 1, wherein said electrically conducting plug is a refractory metal plug.

6. A semiconductor structure according to claim 1, wherein said electrically conducting plug is formed of a material selected from the group consisting of titanium, tantalum, molybdenum and tungsten.

13. A semiconductor structure according to claim 1, wherein said conducting plug comprises an outer glue layer and a plug material therein.

14. A semiconductor structure according to claim 1, wherein said polysilicon gate and said diffusion region being exposed in said via in the absence of said conducting plug.

16. The structure according to claim 1, wherein said gate comprises polysilicon.

7. A method of forming a local interconnect in a semiconductor structure, comprising the step of:

depositing an electrically conducting material in a via exposing at least a portion of a gate, a sidewall spacer adjacent to said gate and a portion of a diffusion region such that said electrically conducting material contacts and provides electrical communication between said gate and said diffusion region, said semiconductor structure comprising said diffusion region in a silicon substrate, said gate being on said substrate juxtaposed to but not contacting said diffusion region, said sidewall spacer being disposed above said diffusion region, said via being in an insulating material on said gate.

8. A method according to claim 7, wherein said diffusion region is an N+ or a P+ region.

9. A method according to claim 7, wherein said insulating material is selected from the group consisting of silicon oxide and silicon nitride.

10. A method according to claim 7, wherein said electrically conducting plug is a metal plug.

11. A method according to claim 7, wherein said electrically conducting plug is preferably a refractory metal plug.

12. A method according to claim 7, wherein said electrically conducting plug is formed of a material selected from the group consisting of titanium, tantalum, molybdenum and tungsten.

15. A method according to claim 7, wherein said gate is a polysilicon gate.

17. The method according to claim 7, wherein said gate comprises polysilicon.