Battery monitoring circuit with storage of charge and discharge accumulation values accessible therefrom

• US 5,965,997 A
• Filed: 08/20/1997
• Issued: 10/12/1999
• Est. Priority Date: 08/20/1997
• Status: Expired due to Term

• Current Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Original Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Inventors: Alwardi, Milad, Heacock, Dave, Matthews, Wallace Edward, Freeman, David Louis
• Primary Examiner(s): Tso, Edward H.
• Application Number:
  US08/915,019
• Time in Patent Office: 783 Days
• Field of Search: 320/112, 320/114, 320/130, 320/132, 320/134, 320/135, 320/136, 320/128, 320/FOR 131, 320/FOR 138, 320/FOR 142, 320/FOR 147, 320/DIG. 18 , 320/DIG. 21, 324/426, 324/427, 324/428
• US Class Current: 320/132
• CPC Class Codes: G01R 31/382 Arrangements for monitoring battery or accumulator variables, e.g. SoC
• CPC Class Codes: G01R 31/3835 involving only voltage measurements
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A battery charge/discharge monitor circuit (10) is operable to be disposed in a battery pack (12) which can be connected to a battery (13). The monitor circuit (10) is operable to be connected to an external CPU (24) or similar system through a single wire communication port (22) for transferring information back and forth. There is also provided an external signal on a line (30) for indicating charge or discharge activity in the monitor circuit (10). The monitor circuit (10) is operable to collect information regarding the amount of charge input to the battery and the length of time that the charge is input to the battery and also the amount of charge that is removed from the battery and the length of time that the charge is removed. This information is stored in a memory block (62) for later access by the external CPU (24). This system also provides offset information to provide some type of compensation for non-linearities of the part. This offset is determined during a calibration operation which operates over a long period of time during a period of inactivity. Regulation circuitry is operable to provide internal regulation to the circuitry with an external JFET (20).

Claims

1. A battery monitoring circuit for monitoring select parameters of a battery having positive and negative terminals, comprising:

a charge determination circuit for determining information relative to the current level input to the battery as a function of time;

a charge accumulation register for storing an accumulated charge value representing the level of current input to the battery over the time that the current level was present, as determined by said charge determination circuit;

a discharge determination circuit for determining information relative to the current level output from the battery as a function of time;

a discharge accumulation register for storing an accumulated discharge value representing the level of current output from the battery over the time that the current level was present, as determined by said discharge determination circuit; and

an input/output interface for allowing an external system to access the contents of said charge accumulation register and discharge accumulation register and the information stored therein.

2. The monitoring circuit of claim 1, and further comprising:

a charge timer for determining the amount of time said charge determination circuit is operating;

a discharge timer for determining the amount of time said discharge determination circuit is operating;

a discharge time register for storing information representing the accumulated time that said discharge timer is operating;

a charge time register for storing information representing the accumulated time that said charge timer is operating; and

wherein said discharge time register and charge time register are accessible by said external system through said Input/output interface.

3. The monitoring circuit of claim 1, wherein a sense resistor is disposed in series with one of said positive and negative terminals of the battery and each of said charge and discharge determining devices comprises:

a voltage-to-frequency converter circuit for converting the voltage across the sense resistor to a pulse stream wherein each pulse represents a predetermined voltage level per unit time and at opposite polarities for each of said charge and discharge determination circuits; and

a counter clocked by said voltage-to-frequency converter pulse stream, the output of said counter stored in the respective one of said charge accumulation and discharge accumulation registers.

4. The monitoring circuit of claim 3, wherein said unit time measurement is one hour.

5. The monitoring circuit of claim 1, and further comprising a sleep device operable to reduce current draw to the monitor circuit in response to a signal from said external system through said Input/output interface and the charge or discharge levels determined by said charge determination and discharge determination circuits being below a predetermined threshold.

6. The monitoring circuit of claim 5, wherein said sleep device includes an internal comparator for comparing the output value from said charge determination and discharge determination devices with a stored sleep threshold value stored in a sleep threshold register and generating a true value indicating activity below a desired level when this value is less than said stored sleep threshold value.

7. The monitoring circuit of claim 6, wherein said sleep threshold register is accessible by said external system through said Input/output interface to allow said external system to input said sleep threshold value to said sleep threshold register.

8. The monitoring circuit of claim 1, and further comprising a calibration circuit for determining the error in said charge determination and discharge determination circuits and storing a calibration value in a calibration value register accessed by said external system through said Input/output interface.

9. The monitoring circuit of claim 8, wherein said calibration circuit operates in response to an external calibration signal received from said external system through said Input/output interface.

10. The monitoring circuit of claim 9, wherein said external calibration signal is stored in a calibration register.

11. The monitoring circuit of claim 9, wherein said calibration circuit operates only when said external calibration signal is received and the output of each of said charge determining and discharge determining circuits is below a predetermined threshold.

12. The monitoring circuit of claim 8, wherein said calibration circuit comprises:

a calibration timer for operating said calibration circuit for a predetermined period of time; and

a difference circuit for determining the accumulated difference between the accumulated outputs of said charge determination and discharge determination circuits for said predetermined period of time.

13. The monitoring circuit of claim 1, wherein said Input/output interface operates to access information stored in said charge accumulation register and said discharge accumulation register only upon a request for such information from said external system.

14. The monitoring circuit of claim 1, wherein said Input/output interface comprises a serial bus data interface.

15. The monitoring circuit of claim 14, wherein said serial bus data interface comprises a single wire interface.

16. The monitoring circuit of claim 15, wherein the battery monitoring circuit and battery are disposed in a battery pack with a minimum of three terminals interfaced thereto, the positive and negative battery terminals and said single wire interface.

17. The monitoring circuit of claim 1, and further comprising an activity determining device for monitoring the output of said charge determination circuit and said discharge determination circuit and, if the outputs of said charge and discharge determining circuits are less than a predetermined threshold value, outputting a signal to said external system through a second Input/output interface indicating a lack of activity, the absence of said signal indicating activity to said external system.

18. A system for monitoring select parameters of a battery having positive and negative terminals, comprising:

a charge determination circuit for determining information relative to the current level input to the battery as a function of time;

a charge accumulation register for storing an accumulated charge value representing the level of current input to the battery over the time that the current level was present, as determined by said charge determination circuit;

a discharge determination circuit for determining information relative to the current level output from the battery as a function of time;

a discharge accumulation register for storing an accumulated discharge value representing the level of current output from the battery over the time that the current level was present, as determined by said discharge determination circuit;

a CPU for determining the parameters of the battery utilizing information in said charge determination circuit, said charge accumulation register, said discharge determination circuit and said discharge accumulation register; and

an input/output interface for interfacing said CPU to the contents of said charge accumulation register and discharge accumulation register and the information stored therein.

19. A method for monitoring select parameters of a battery having positive and negative terminals, comprising:

determining information relative to the current input to the battery as a function of time with a charge determination circuit;

storing an accumulated charge value representing the amount of current input to the battery over time in a charge accumulation register, as determined by the charge determination circuit;

determining information relative to the current output from the battery as a function of time with a discharge determination circuit;

storing an accumulated discharge value representing the amount of current output from the battery as a function of time in a discharge accumulation register, as determined by the discharge determination circuit; and

providing an interface with an external system to allow access thereby to the charge accumulation register and discharge accumulation register and the information stored therein.

20. The method of claim 19, and further comprising the steps of:

determining with a charge timer the amount of time the charge determination circuit is operating;

determining with a discharge timer the amount of time the discharge determination circuit is operating;

storing information in a discharge time register representing the accumulated time that the discharge timer is operating;

storing information in a charge time register representing the accumulated time that the charge timer is operation; and

wherein the discharge time register and charge time register are accessible by the external system through the step of providing.

21. The method of claim 19, and further comprising the steps of disposing a sense resistor in series with one of the positive and negative terminals of the battery and the step of determining information relative to the current input and determining information relative to the current output each comprising the steps of:

providing a voltage-to-frequency converter circuit;

converting the voltage across the sensor resister to a pulse stream with the voltage-to-frequency converter circuit wherein each pulse represents a predetermined voltage level per unit of time and at opposite polarities for each of the charge and discharge determination circuits; and

clocking a counter with the voltage-to-frequency converter pulse stream, and storing the output of the counter in the respective one of the charge accumulation and discharge accumulation registers.

22. The method of claim 21, wherein a unit of time measurement is one hour.

23. The method of claim 19, and further comprising the step of reducing current draw to the overall operation in response to a signal from the external system and the charge or discharge levels determined by the charge determination and discharge determination circuits being below a predetermined threshold.

24. The method of claim 23, wherein the step of reducing current draw includes the steps of comparing the output value for the charge determination and discharge determination devices with a stored sleep threshold value stored in a sleep threshold register and then generating a true value indicating activity below a desired level when this value is less than the stored sleep threshold value.

25. The method of claim 24, wherein the sleep threshold register is accessible by the CPU device to allow the external system to input the sleep threshold value to the sleep threshold register.

26. The method of claim 19, and further comprising the step of determining the error in the charge determination and discharge determination circuits and storing a calibration value in a calibration value register accessible by the external system.

27. The method of claim 26, wherein the step of determining the error operates in response to a calibration signal received from the external system.

28. The method of claim 27, wherein the calibration signal is stored in a calibration register.

29. The method of claim 27, wherein the step of determining the error operates only when the calibration signal is received from the CPU device and the output of each charge determining and discharge determining circuits is below a predetermined threshold.

30. The method of claim 27, wherein the step of determining the error comprises the steps of:

controlling the operation of the calibration circuit with a calibration timer and operating the calibration circuit for a predetermined period of time as defined by the calibration timer; and

determining the accumulated difference between the accumulated outputs of the charge determination and discharge determination circuits for the predetermined period of time.

31. The method of claim 19, and further comprising the step of monitoring the output of the charge determination circuit and the discharge determination circuit and, if the outputs of the charge and discharge determination circuits are less than a predetermined threshold value, outputting a signal to the CPU device indicating a lack of activity, the absence of the signal indicating activity to the CPU device.