Integrated photosensing device for active pixel sensor imagers

• US 5,969,337 A
• Filed: 04/29/1997
• Issued: 10/19/1999
• Est. Priority Date: 04/29/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Yiannoulos, Aris Antony
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Luu, Thanh X.
• Application Number:
  US08/846,967
• Time in Patent Office: 903 Days
• Field of Search: 250/214.1, 250/208.1, 257/292, 257/291, 257/290
• US Class Current: 250/214.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70

Abstract

An integrated photosensing device includes a three-terminal photosensing device integrated within a photo-integrator semiconductor integrated circuit. The photosensing device includes a Metal-Oxide-Semiconductor (MOS) capacitor merged with a junction diode, both of which are integrated on a semiconductor substrate. The photo-integrator semiconductor integrated circuit includes a voltage buffer and a number of switches for configuring the photo-integrator during an operating cycle that includes three phases. The circuit resets during the first phase and integrates during the second phase. During the third phase, the circuit forces the output impedance of the photosensing device to increase such that the signal output of the circuit is boosted. Various embodiments are described for the present invention which disclose several buffer and switch configurations for buffering the output and providing the bias requirements of the photosensing device. In one such embodiment, the voltage buffer is implemented as a source-follower circuit having an output voltage that is used to bias the MOS capacitor of the photosensing device into accumulation as opposed to using a fixed bias source. In another embodiment, an additional switch is included to separate the output node of the photo-integrator circuit into two separate node portions. These node portions are used to time share certain elements of the photo-integrator circuit when used in imaging arrays having multiple sites.

Claims

1. A photo-integrator circuit operable in a first, second, and third phase, said photo-integrator circuit comprising:

a photosensing device including a semiconductor substrate, a junction diode having a first electrical side and a second electrical side, and a Metal-Oxide-Semiconductor (MOS) capacitor having a first electrical side and a second electrical side, said junction diode and said MOS capacitor being adjacently integrated on said substrate, said photosensing device further including a body terminal contacting a region of said substrate, said region being defined by said first electrical side of said junction diode and said first electrical side of said MOS capacitor, a gate terminal contacting said second electrical side of said MOS capacitor, and a diode terminal contacting said second electrical side of said junction diode; and

a switch means coupled to said diode terminal of said photosensing device,

said MOS capacitor being operable to be biased into a first mode during the first phase, said junction diode being operable to be reverse biased during the first phase, said MOS capacitor being further operable to be biased into a second mode during the second phase, the second phase continuing for a given time interval, said photosensing device being operable to be illuminated during said given time interval, said MOS capacitor being further operable to be biased into said first mode during the third phase, wherein said first mode is an accumulation mode,

said photosensing device being operable to generate a voltage response between said diode terminal and said body terminal during the second phase, said photosensing device being further operable to boost said voltage response during the third phase.

2. The photo-integrator circuit according to claim 1, wherein:

said switch means includes an open and a closed position;

said MOS capacitor is responsive to a first voltage signal applied between said gate terminal and said body terminal for biasing into said accumulation mode during the first phase;

said switch means is operable to transition to said closed position during the first phase, said switch means is further operable in said closed position to couple said diode terminal to a second voltage signal, wherein said junction diode is responsive to said second voltage signal applied between said diode terminal and said body terminal for reverse biasing during the first phase;

said switch means is operable to transition to said open position prior to completion of the first phase, wherein said MOS capacitor is responsive to a third voltage signal applied between said gate terminal and said body terminal for biasing into said second mode during the second phase for said given time interval; and

wherein said MOS capacitor is responsive to a fourth voltage signal applied between said gate terminal and said body terminal for biasing into said accumulation mode during the third phase.

3. The photo-integrator circuit according to claim 2, wherein said second electrical side of said junction diode comprises a diffused layer disposed on a surface of said region, wherein said MOS capacitor further includes an inversion layer formed during said second mode, and wherein said second electrical side of said junction diode electrically and physically contacts said inversion layer of said MOS capacitor.

4. The photo-integrator circuit according to claim 1, wherein said switch means is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), said MOSFET being operable in a triode region of an operating characteristic.

5. The photo-integrator circuit according to claim 1, wherein said switch means is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having a source terminal and a gate terminal, said diode terminal of said photosensing device being coupled to said source terminal of said MOSFET, said MOSFET being operable in a saturation region of an operating characteristic, wherein a voltage value at said diode terminal is controlled by a voltage applied at said gate terminal of said MOSFET.

6. The photo-integrator circuit according to claim 3, further comprising a voltage buffer having an input terminal, a reference terminal, and an output terminal, said input terminal being coupled to said diode terminal, said reference terminal being coupled to said body terminal, said voltage buffer being operable to buffer said voltage response of said photosensing device, said voltage buffer being further operable to generate a buffered voltage response at said output terminal.

7. The photo-integrator circuit according to claim 6, wherein said voltage buffer comprises a source follower circuit.

8. The photo-integrator circuit according to claim 7, wherein said source follower circuit includes:

a Metal-Oxide-Semiconductor (MOS) field effect transistor having a source terminal, a drain terminal, and a gate terminal, said gate terminal of said MOS field effect transistor being coupled to said diode terminal of said photosensing device, said source terminal being coupled to said gate terminal of said photosensing device, said drain terminal being coupled to said second voltage signal; and

a current-source load coupled between said source terminal of said MOS field effect transistor and said body terminal of said photosensing device,

said source follower circuit being operable to be biased by said second voltage signal, and

wherein said buffered voltage response has a value equivalent to a voltage value across said current-source load.

9. The photo-integrator circuit according to claim 8, wherein said source-follower circuit is operable to bias said MOS capacitor into said accumulation mode via said output terminal.

10. The photo-integrator circuit according to claim 9, further comprising:

a voltage source; and

a second switch means having an open and a closed position, said second switch means being operable in said closed position to couple said voltage source between said gate terminal and said body terminal of said photosensing device,

wherein said voltage source is operable to bias said MOS capacitor into said second mode while said second switch means is in said closed position, and wherein a bias voltage of said voltage source is substantially equivalent to said third voltage signal.

11. The photo-integrator circuit according to claim 10, further comprising:

an output node including a first node portion and a second node portion, said first node portion being common to said source terminal of said MOS field effect transistor and said gate terminal of said photosensing device, said second node portion being common to said current-source load and one side of said second switch means; and

a third switch means coupled between said first node portion and said second node portion, said third switch means having an open and a closed position, said third switch means being in said open position during the second phase, and said second switch means being in said closed position during the first phase and the third phase.

12. The photo-integrator circuit according to claim 1, wherein said second mode is an inversion mode.

13. The photo-integrator circuit according to claim 1, wherein said second mode is a depletion mode.

14. The photo-integrator circuit according to claim 10, wherein said second mode is an inversion mode.

15. The photo-integrator circuit according to claim 10, wherein said second mode is a depletion mode.

16. An integrated imaging array having a plurality of sets of array sites, each array site comprising:

a photosensing device including a semiconductor substrate, a junction diode having a first electrical side and a second electrical side, and a Metal-Oxide-Semiconductor (MOS) capacitor having a first electrical side and a second electrical side, said junction diode and said MOS capacitor being adjacently integrated on said substrate, said photosensing device further including a body terminal contacting a region of said substrate, said region being defined by said first electrical side of said junction diode and said first electrical side of said MOS capacitor, a gate terminal contacting said second electrical side of said MOS capacitor, and a diode terminal contacting said second electrical side of said junction diode; and

a first switch means coupled to said diode terminal of said photosensing device,

said MOS capacitor being operable to be biased into a first mode during a first phase in response to a first voltage signal applied between said gate terminal and said body terminal,

said junction diode being operable to be reverse biased during said first phase in response to a second voltage signal applied between said diode terminal and said body terminal,

said MOS capacitor being further operable to be biased into a second mode during a second phase in response to a third voltage signal applied between said gate terminal and said body terminal, said second phase continuing for a given time interval, said photosensing device being operable to be illuminated during said given time interval,

said MOS capacitor being further operable to be biased into said first mode during a third phase in response to a fourth voltage signal applied between said gate terminal and said body terminal, wherein said first mode is an accumulation mode,

said photosensing device being operable to generate a voltage response between said diode terminal and said body terminal during said second phase, said photosensing device being further operable to boost said voltage response during said third phase.

17. The integrated imaging array according to claim 16, further comprising a voltage buffer having an input terminal, a reference terminal, and an output terminal, said input terminal being coupled to said diode terminal, said reference terminal being coupled to said body terminal, said voltage buffer being operable to buffer said voltage response of said photosensing device, said voltage buffer being further operable to generate a buffered voltage response at said output terminal.

18. The integrated imaging array according to claim 17, further comprising:

a second switch means coupled to said gate terminal of said photosensing device;

wherein said voltage buffer comprises a source follower circuit, said source follower circuit including

a Metal-Oxide-Semiconductor (MOS) field effect transistor having a source terminal, a drain terminal, and a gate terminal, said gate terminal of said MOS field effect transistor being coupled to said diode terminal of said photosensing device, said source terminal being coupled to said gate terminal of said photosensing device, said drain terminal being coupled to said second voltage signal, and

a current-source load coupled between said source terminal of said MOS field effect transistor and said body terminal of said photosensing device;

said source follower circuit being operable to be biased by said second voltage signal, said source-follower circuit being further operable to bias said MOS capacitor into said accumulation mode via said output terminal, and wherein said buffered voltage response has a value equivalent to a voltage value across said current-source load.

19. The integrated imaging array according to claim 17, wherein said voltage buffer comprises a source follower circuit, said source follower circuit including a Metal-Oxide-Semiconductor (MOS) field effect transistor having a source terminal, a drain terminal, and a gate terminal, said gate terminal of said MOS field effect transistor being coupled to said diode terminal of said photosensing device, said source terminal being coupled to said gate terminal of said photosensing device, said drain terminal being coupled to said second voltage signal, wherein said source follower circuit is operable to be biased by said second voltage signal, and said source-follower circuit is further operable to bias said MOS capacitor into said accumulation mode via said output terminal.

20. The integrated imaging array according to claim 19, wherein each array site in one of said plurality of sets is operable to be sequentially addressed, and wherein each array site in one of said plurality of sets is further operable to time share a single current-source load, said current-source load being coupled between said source terminal of said MOS field effect transistor and said body terminal of said photosensing device.

21. The integrated imaging array according to claim 20, wherein each array site in one of said plurality of sets is further operable to time share a single second switch means, said second switch means being coupled to said gate terminal of said photosensing device.

22. The photo-integrator circuit according to claim 16, wherein said second mode is an inversion mode.

23. The photo-integrator circuit according to claim 16, wherein said second mode is a depletion mode.

24. An integrated imaging array having a plurality of sets of array sites, each array site comprising:

a photosensing device including a semiconductor substrate, a junction diode having a first electrical side and a second electrical side, and a Metal-Oxide-Semiconductor (MOS) capacitor having a first electrical side and a second electrical side, said junction diode and said MOS capacitor being adjacently integrated on said substrate, said photosensing device further including a body terminal contacting a region of said substrate, said region being defined by said first electrical side of said junction diode and said first electrical side of said MOS capacitor, a gate terminal contacting said second electrical side of said MOS capacitor, and a diode terminal contacting said second electrical side of said junction diode, said MOS capacitor being operable to be biased into a first mode during a first phase, said junction diode being operable to be reverse biased during said first phase, said MOS capacitor being further operable to be biased into a second mode during a second phase, said second phase continuing for a given time interval, said photosensing device being operable to be illuminated during said given time interval, said MOS capacitor being further operable to be biased into said first mode during a third phase, said photosensing device being operable to generate a voltage response between said diode terminal and said body terminal during said second phase, said photosensing device being further operable to boost said voltage response during said third phase;

a first switch means coupled to said diode terminal of said photosensing device;

a source follower circuit including

a Metal-Oxide-Semiconductor (MOS) field effect transistor having a source terminal, a drain terminal, and a gate terminal, said gate terminal of said MOS field effect transistor being coupled to said diode terminal of said photosensing device, said source terminal being coupled to said gate terminal of said photosensing device, and

a current-source load coupled between said source terminal of said MOS field effect transistor and said body terminal of said photosensing device,

said source follower circuit being operable to buffer said voltage response;

a second switch means coupled to said source terminal of said MOS field effect transistor and to said gate terminal of said photosensing device;

an output node comprising a first node portion and a second node portion, said first node portion being common to said source terminal of said MOS field effect transistor and said gate terminal of said photosensing device, said second node portion being common to said current-source load and one side of said second switch means; and

a third switch means coupled between said first node portion and said second node portion,

wherein each array site in one of said plurality of sets is operable during said first and third phase to be sequentially addressed by closing said third switch means, and wherein each array site in one of said plurality of sets is further operable to time share said second node portion when addressed.

25. The photo-integrator circuit according to claim 24, wherein said first mode is an accumulation mode and said second mode is an inversion mode.

26. The photo-integrator circuit according to claim 24, wherein said first mode is an accumulation mode and said second mode is a depletion mode.