Single chip remote access processor
First Claim
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1. A single chip remote access processor for receiving and transmitting data packets having headers with destination addresses, the processor comprising:
- a plurality of communication interface units adapted to transmit and receive the data packets and comprising a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit;
a multi-channel direct memory access (DMA) controller which is coupled to the plurality of communication interface units and comprises a plurality of channels and a contents addressable memory (CAM), wherein each channel comprises a transmit queue and a receive queue and wherein the CAM comprises a contents compare input coupled to the receive queues so as to receive the destination address of each received data packet and comprises a compare output that identifies which of a plurality of receive linked lists each data packet received by the receive queues is to be appended based on a comparison of the respective destination address;
a central processing unit (CPU) is adapted to maintain a transmit linked list of transmit buffer memory descriptors (BMDs) for each channel of the DMA controller and to maintain the plurality of receive linked lists of receive BMDS, wherein each transmit BMD corresponds to a data packet to be transmitted through the respective channel and wherein each receive BMD corresponds to a data packet received through one of the channels.
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Abstract
A single chip integrated remote access processor circuit has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit. A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units.
159 Citations
18 Claims
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1. A single chip remote access processor for receiving and transmitting data packets having headers with destination addresses, the processor comprising:
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a plurality of communication interface units adapted to transmit and receive the data packets and comprising a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit; a multi-channel direct memory access (DMA) controller which is coupled to the plurality of communication interface units and comprises a plurality of channels and a contents addressable memory (CAM), wherein each channel comprises a transmit queue and a receive queue and wherein the CAM comprises a contents compare input coupled to the receive queues so as to receive the destination address of each received data packet and comprises a compare output that identifies which of a plurality of receive linked lists each data packet received by the receive queues is to be appended based on a comparison of the respective destination address; a central processing unit (CPU) is adapted to maintain a transmit linked list of transmit buffer memory descriptors (BMDs) for each channel of the DMA controller and to maintain the plurality of receive linked lists of receive BMDS, wherein each transmit BMD corresponds to a data packet to be transmitted through the respective channel and wherein each receive BMD corresponds to a data packet received through one of the channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18)
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14. A remote access processor comprising:
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an internal transfer bus; a plurality of communication interface units comprising a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit, wherein the telephony coder-decoder interface unit comprises a serial interface for receiving modulated digital samples; a multi-channel direct memory access (DMA) controller coupled to the internal transfer bus and having a first channel coupled to the LAN interface unit, a second channel coupled to the multi-protocol SWAN interface unit and a third channel coupled to the telephony coder-decoder interface unit; a central processing unit (CPU) coupled to the internal transfer bus which is adapted to receive a first data packet through the first or second channel of the DMA controller, modulate the first data packet for transmission through the telephony coder-decoder interface unit and route the modulated first data packet to the telephony coder-decoder interface unit, through the third channel of the DMA controller and is adapted to receive the modulated digital samples from the telephony coder-decoder through the third channel of the DMA controller, demodulate the digital samples, translate the demodulated digital samples into a second data packet, and route the second data packet to the LAN interface unit or the multi-protocol SWAN interface unit, through the first and second channels, respectively, of the DMA controller; a memory coupled to the DMA controller and the CPU; and wherein the PCI interface unit is coupled to the internal transfer bus.
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15. A method of routing a data packet in a circuit comprising a plurality of communication interfaces and a direct memory access (DMA) controller having multiple channels, comprising:
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coupling the plurality of communication interfaces to corresponding channels of the DMA controller; receiving the data packet at a first of the plurality of communication interfaces; passing the data packet to the DMA channel that is coupled to the first communication interface; storing the data packet in a buffer memory; maintaining a plurality of receive linked buffer memory description (BMD) lists; maintaining a transmit linked BMD list for each channel of the DMA controller; determining a destination of the data packet; appending a buffer memory descriptor (BMD), which corresponds to the data packet, to at least one of the receive linked BMD lists, as a function of the destination; appending the BMD to the transmit linked BMD list of a second channel of the DMA controller as a function of the destination; passing the data packet from the buffer memory to the second channel; and transmitting the data packet from the second channel to the communication interface that is coupled to the second channel. - View Dependent Claims (16, 17)
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Specification