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Single chip remote access processor

  • US 5,970,069 A
  • Filed: 04/21/1997
  • Issued: 10/19/1999
  • Est. Priority Date: 04/21/1997
  • Status: Expired due to Term
First Claim
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1. A single chip remote access processor for receiving and transmitting data packets having headers with destination addresses, the processor comprising:

  • a plurality of communication interface units adapted to transmit and receive the data packets and comprising a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit;

    a multi-channel direct memory access (DMA) controller which is coupled to the plurality of communication interface units and comprises a plurality of channels and a contents addressable memory (CAM), wherein each channel comprises a transmit queue and a receive queue and wherein the CAM comprises a contents compare input coupled to the receive queues so as to receive the destination address of each received data packet and comprises a compare output that identifies which of a plurality of receive linked lists each data packet received by the receive queues is to be appended based on a comparison of the respective destination address;

    a central processing unit (CPU) is adapted to maintain a transmit linked list of transmit buffer memory descriptors (BMDs) for each channel of the DMA controller and to maintain the plurality of receive linked lists of receive BMDS, wherein each transmit BMD corresponds to a data packet to be transmitted through the respective channel and wherein each receive BMD corresponds to a data packet received through one of the channels.

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