Silicided shallow junction transistor formation and structure with high and low breakdown voltages

CAFC
  • US 5,973,372 A
  • Filed: 12/06/1997
  • Issued: 10/26/1999
  • Est. Priority Date: 12/06/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. In an integrated circuit in and on a silicon substrate having an active region including a field effect transistor with a source and a drain and a gate, all of which a conductive contact is made comprising:

  • a single crystalline silicon substrate with a upper surface region;

    a shallow junction for each of the source and drain of the transistor underlying said upper surface of the silicon substrate;

    a metal silicide layer having a lower surface disposed adjacent the shallow junction of each of the source and drain in the silicon substrate and above said upper surface of the silicon substrate; and

    an epitaxial silicon layer disposed between said upper silicon surface and said lower surface of metal silicide and adjacent the shallow junction of each of the source and drain whereby the metal silicide does not extend below the upper silicon surface and encroach upon the shallow junction of each of the source and the drain.

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