Capacitor on ultrathin semiconductor on insulator

• US 5,973,382 A
• Filed: 05/23/1997
• Issued: 10/26/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Sung, John Y., Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/862,575
• Time in Patent Office: 886 Days
• Field of Search: 257/532, 257/296, 257/298, 257/379, 257/312
• US Class Current: 257/532
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78657 SOS transistors

Abstract

An integrated circuit is provided which comprises: an insulating substrate; a semiconductor layer formed on the insulating substrate; a MOSFET including a source, drain and channel formed in the silicon layer and a gate adjacent to the channel; a gate terminal; and a conductor interconnecting the source and drain so as to maintain them at a common potential.

Claims

1. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and

a conductor interconnecting the source and drain so as to maintain them at a common potential;

wherein the channel is fully depleted for a gate bias voltage that has not surpassed a threshold voltage of the MOSFET structure.

2. The integrated circuit of claim 1 wherein the insulating substrate is sapphire.

3. The integrated circuit of claim 1 wherein the silicon layer is approximately 1000 Angstroms thick.

4. The integrated circuit of claim 1 wherein the silicon layer is in the range 100 Angstroms thick to 1500 Angstroms thick.

5. The integrated circuit of claim 1 wherein the source and drain extend to the insulating substrate.

6. The integrated circuit of claim 1 and further including a control voltage terminal coupled to one of said gate or said commonly connected source/drain.

7. The integrated circuit of claim 1 wherein the silicon layer surrounds the MOSFET structure.

8. The integrated circuit of claim 1 wherein the silicon layer is substantially less than 1000 Å

thick and is greater than or equal to 100 Å

thick.

9. The integrated circuit of claim 1 wherein the MOSFET structure is an n-type device structure.

10. The integrated circuit of claim 1 wherein the MOSFET structure is a p-type device structure.

11. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and

a conductor interconnecting the source and drain so as to maintain them at a common potential;

wherein the MOSFET structure is an n-type device structure in which the channel is fully depleted for a negative gate bias voltage below a threshold voltage of the MOSFET structure.

28. The integrated circuit of claim 11, or 12 wherein

the source and drain extend to the insulating substrate.

12. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and

a conductor interconnecting the source and drain so as to maintain them at a common potential;

wherein the MOSFET structure is a p-type devce structure in which the channel is fully depleted for a negative gate bias voltage above a threshold voltage of the MOSFET structure.

13. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and

a first electrical contact to the first portion; and

a second electrical contact to the second portion;

wherein the first portion is fully depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure sharply transitions.

17. The integrated circuit of claims 13, 14 and 15 wherein the second portion extends to the insulating substrate.

18. The integrated circuit of claim 13 wherein the first impurity type is one of p-type or n-type and the second impurity type is the other of p-type or n-type.

21. The integrated circuit of claim 13, 14 or 15 wherein the silicon layer surrounds the second portion.

22. The integrated circuit of claim 13 wherein the first electrical contact includes a metal layer which overlays an oxide layer.

23. The integrated circuit of claim 13 wherein the first electrical connection includes a metal layer which overlays an oxide layer and the lightly doped regions extend partially beneath the first electrical connection.

24. The integrated circuit of claim 13, 14 or 15 wherein the insulating substrate is sapphire.

25. The integrated circuit of claim 13 wherein the layer of silicon is between 100 Å

thick and 1500 Å

thick.

26. The integrated circuit of claim 13 wherein the layer of silicon is approximately 1000 Å

thick.

27. The integrated circuit of claim 13 wherein the layer of silicon is substantially less than 1000 Å

thick and greater than or equal to 100 Å

thick.

14. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and

a first electrical contact to the first portion; and

a second electrical contact to the second portion;

wherein the first impurity is n-type and the second impurity is p-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is below the threshold voltage of the capacitor structure.

16. The integrated circuit of claims 14 or 15 wherein the silicon layer is between 100 Å

thick and 1500 Å

thick.

15. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and

a first electrical contact to the first portion; and

a second electrical contact to the second portion;

wherein the first impurity is p-type and the second impurity is n-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is above threshold voltage of the capacitor structure.

19. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a MOSFET structure including, a channel, a source adjacent to the channel, and a drain adjacent to the channel, which are formed in said silicon layer and including a gate which overlays the channel; and

a conductor interconnecting the source and drain so as to maintain them at a common potential;

wherein the channel is fully depleted for a gate bias voltage that has not surpassed a threshold voltage of the MOSFET structure.

20. An integrated circuit capacitor comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween; and

a first electrical contact to the first portion; and

a second electrical contact to the second portion;

wherein the first portion is filly depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure gharply transitions.