Computer system having organization for multiple condition code setting and for testing instruction out-of-order

• US 5,983,335 A
• Filed: 04/30/1997
• Issued: 11/09/1999
• Est. Priority Date: 06/13/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dwyer, Harry III
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/841,550
• Time in Patent Office: 923 Days
• Field of Search: 395/800.23, 395/800.24, 395/390, 395/391, 395/392, 395/393, 395/566, 711/125, 711/149, 711/217, 712/23, 712/24, 712/225, 712/214, 712/215, 712/216
• US Class Current: 712/23
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 11/3461 Trace driven simulation
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.

Claims

1. A computer system comprising:

multiple functional units for executing instructions;

issuing means for issuing instructions for processing by said functional units and including an instruction issue unit;

a buffer;

one or more register files;

a cache store coupled between main memory and said functional units;

an interconnection network coupling said functional units, said register files, and said instruction issue unit;

means for concurrently executing multiple out-of-order instructions;

means for attaching an I-Group comprising an instruction and a tag, a read-vector, a write vector, and a type vector as control bits for instructional use by the system for permitting the hardware of the system to schedule concurrently and on a short cycle time basis multiple, possibly out-of-order, instruction issuances to multiple functional units for execution and to transfer I-Groups to the buffer or for scheduling by said issue unit;

an instruction scheduling mechanism and in which the issue unit includes assigning means for concurrently assigning and issuing independent, multiple, out-of-order instructions contained in the instruction scheduling mechanism provided by said issue unit to the multiple functional units for execution; and

ports connecting the issue unit to the multiple functional units,

wherein said assigning means includes prioritization means for prioritizing eligible instructions by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it so that independent instructions eligible for transfer may outnumber available functional units for paths via a port through which instructions may be transferred.

2. A computer system according to claim 1 further comprising:

a memory; and

means for ordering the execution process including;

a. means for fetching multiple instructions from the memory at once and generating an I-Group for each instruction;

b. means for concurrently decoding multiple fields of information in an instruction as part of the I-Group generation; and

c. means for transferring the resulting I-Groups to said issue unit, but if the issue unit is full, to the buffer.

3. A computer system according to claim 1 wherein the assigning means include permanent assignment means for making the assignment of a port-type permanent.

4. A computer system according to claim 3 wherein said permanent assignment means include a type vector applicable to a particular kind of multiple functional units.

5. A computer system according to claim 1 wherein the assigning means include dynamic port assignment means for making the assignment of a port-type dynamic.

6. A computer system according to claim 5 further comprising means to determine the availability of functional units and wherein dynamic port assignment means include means to provide a match for each machine cycle which is dependent upon an availability determination and which include means for assigning a port type and for then selecting an instruction which can be assigned to an available functional unit.

7. A computer system according to claim 1 wherein assigning means include matching means for transferring independent instructions to OPEN ports of matching types for prioritizing eligible instructions in order that independent instructions eligible for transfer may outnumber available functional units or paths via a port through which instructions may be transferred.

8. A computer system according to claim 7 wherein matching means include means for connecting an OPEN port to an available functional unit of the correct type for executing the eligible instruction.

9. A computer system according to claim 1 wherein said functional units include a plurality of functional units of the same type to provide multiple copy execution units of the same type for concurrently executing instructions requiring execution of the same type of function.

10. A computer system comprising:

multiple functional units for executing instructions;

issuing means including an issue unit for issuing instructions for processing by said functional units;

one or more register files;

a main memory store;

a cache store coupled between main memory and said functional units;

an interconnection network coupling said functional units, said 11 register files, and said instruction issue unit;

means for currently executing multiple out-of-order instructions; and

instruction scheduling means for concurrently assigning and transferring independent, multiple, out-of-order instructions to multiple functional units for execution and wherein the number of independent instructions eligible for transfer may outnumber available functional units or paths through which instructions may be transferred, and including, assigning means for prioritizing eligible instructions in hardware by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it.

11. A computer system according to claim 10 wherein means for prioritizing eligible instructions include means for permanently assigning a port-type.

12. A computer system according to claim 11 wherein said permanent assignment means include a type vector applicable to a particular kind of multiple functional units.

13. A computer system according to claim 10 wherein the assignment means include dynamic port assignment means for making the assignment of a port-type dynamic.

14. A computer system according to claim 13 further including means to check the availability of functional units for each machine cycle and wherein dynamic port assignment means include means to provide a match for each machine cycle which is dependent upon an availability check of available function units which are not busy, to assign a port type and then to select an instruction which can be assigned to an available functional unit.

15. A computer system according to claim 10 wherein assigning means include matching means to transfer independent instructions to OPEN ports of matching types for prioritizing eligible instructions.

16. A computer system according to claim 15 wherein matching means include means for connecting an OPEN port to an available functional unit of the correct type for executing the eligible instruction.

17. A computer system according to claim 10 wherein said functional units include a plurality of functional units of the same type to provide multiple copy execution units of the same type for concurrently executing instructions requiring executing the same type of function.