Kit for electrically isolating collimator of PVD chamber, chamber so modified, and method of using

• US 5,985,102 A
• Filed: 08/06/1997
• Issued: 11/16/1999
• Est. Priority Date: 01/29/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leiphart, Shane P.
• Primary Examiner(s): MCDONALD, RODNEY GLENN
• Application Number:
  US08/907,116
• Time in Patent Office: 832 Days
• Field of Search: 204/192.12, 204/192.3, 204/298.11, 204/298.06, 204/192.17, 438/584, 438/597, 438/674, 438/675
• US Class Current: 204/192.12
• CPC Class Codes: C23C 14/046 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 14/34 Sputtering
• CPC Class Codes: H01J 37/32706 Polarising the substrate
• CPC Class Codes: H01J 37/34 operating with cathodic sputtering H01J37/36 takes precedence ; methods of cathodic sputtering C23C14/34
• CPC Class Codes: H01J 37/3447 Collimators, shutters, apertures

Abstract

A collimator is mounted within a sputter chamber and is interposed between a sputter target and a wafer to be coated with a thin film of the sputtered material. A shield extends around the perimeter of the volume between the collimator and the wafer. The collimator and shield of the present invention are preferably mounted within the sputter chamber in a manner so that they are electrically insulated from the chamber and able to take on a floating electrical potential associated with the potential of the plasma generated within the sputter chamber. A kit for simply and robustly effecting the mounting of the collimator and shield is disclosed. More uniform deposition and surface planarity of target material on the wafer are achieved with the floating collimator when employed with the floating shield structure.

Claims

1. An apparatus for sputter deposition of a material on a semiconductor wafer, comprising:

a grounded chamber adapted for creation of a vacuum therein and provided with a supply of an ionizable gas;

a negatively-biased target of said material disposed in said chamber;

a semiconductor wafer support disposed in said chamber spaced from said target;

a collimator interposed between said target and said wafer support; and

structure for electrically isolating said collimator from said grounded chamber, said structure for electrical isolating including an outer receiving member including at least an electrically non-conductive surface portion and secured to a grounded structural element of said chamber, and an inner collimator adaptor member supporting said collimator and borne on said electrically non-conductive surface portion of said outer receiving member.

2. The apparatus of claim 1, wherein said outer receiving member comprises an aluminum receiving ring including a wall portion having a radially inwardly-extending, substantially annular flange projecting therefrom, said at least an electrically non-conductive surface portion comprising anodization extending at least along an upper annular surface of said annular flange.

3. The apparatus of claim 2, wherein said inner collimator adaptor member comprises an electrically conductive adaptor ring including an adaptor ring wall portion defining a collimator receiving cavity therewithin and a radially outwardly-extending, substantially annular adaptor ring flange projecting therefrom, said adaptor ring flange resting upon said at least an electrically non-conductive surface portion of said receiving ring flange.

4. The apparatus of claim 3, further including an annular, electrically conductive shield extending about a chamber volume located between said collimator and said semiconductor wafer support, said annular shield being suspended from said adaptor ring.

5. The apparatus of claim 4, further including a shield mounting ring at an upper extent of said shield, said shield mounting ring being secured to said adaptor ring.

6. The apparatus of claim 5, wherein said adaptor ring further includes a substantially annular lip projecting radially inwardly from said adaptor ring wall portion, said shield mounting ring is secured to said lip by bolts extending downwardly through said lip, and further including a cover ring disposed over said bolts.

7. The apparatus of claim 3, further including an annular, electrically conductive shield extending about a chamber volume located between said collimator and said semiconductor wafer support, said annular shield being suspended from said structural element of said grounded chamber in electrical communication therewith.

8. The apparatus of claim 2, wherein said anodization is of a thickness of about 6 mils.

9. The apparatus of claim 8, wherein said wall portion of said aluminum receiving ring includes bolt holes extending therethrough, said aluminum receiving ring is secured to said structural element of said grounded chamber by bolts extending through said bolt holes and into said member, and the entire exterior surface of said aluminum receiving ring is anodized.

10. A method for sputter deposition of a material on a semiconductor wafer, comprising:

providing a semiconductor wafer in a chamber, at least a portion of which chamber is at a first potential;

providing a source of said material for said deposition spaced from said wafer in said chamber;

sputtering said material with a gas plasma resident in said chamber to produce sputtered material particles;

collimating trajectories of said sputtered material particles to features on a surface of said wafer in electrical isolation from said first potential to form a film of said material on said wafer; and

substantially laterally enclosing a chamber volume between a location of said collimating and said semiconductor wafer with a conductive shield in electrical isolation from said first potential.

11. The method of claim 10, further comprising maintaining said source of said material at a second potential different from said first potential, and maintaining said wafer at a third potential different from said first potential.

12. The method of claim 11, wherein said first potential comprises ground.

13. A method for sputter deposition of a material on a semiconductor wafer including aspect-ratio features on a surface thereof, comprising:

providing a chamber having at least a portion thereof at a first potential;

providing a semiconductor wafer including said aspect-ratio features within said chamber at a second potential different from said first potential;

providing a source of said material for said deposition spaced from said wafer in said chamber;

sputtering said material with a gas plasma resident in said chamber to produce particles of sputtered material;

collimating trajectories of said particles of sputtered material to features on the surface of said wafer to form a film of said material on said wafer;

substantially laterally enclosing a chamber volume between a location of said collimating and said semiconductor wafer with a conductive shield in electrical isolation from said first and second potentials; and

substantially reducing pinch off of said material proximate entry regions to said aspect ratio features with said second potential.

14. The method of claim 13, wherein said pinch off is substantially reduced through sputtering of deposited material from said entry regions attributable to said second potential.

15. The method of claim 14, further including collimating said trajectories of sputtered material particles in electrical isolation from said first and second potentials.

16. The method of claim 15, further including maintaining said gas plasma at a potential and maintaining said conductive shield at a floating potential.

17. A method for sputter deposition of a material on a semiconductor wafer including recesses in a surface thereof, comprising:

providing said semiconductor wafer in a chamber to produce sputtered material particles;

providing a source of said material for said deposition spaced from said wafer in said chamber;

sputtering said material with a gas plasma resident in said chamber to produce sputtered material particles;

maintaining said gas plasma at a potential; and

collimating trajectories of said sputtered material particles to features on the surface of said wafer at a potential associated with said potential of said gas plasma to form a film of said material on said wafer and within said recesses while substantially surrounding a volume in said chamber between a location of said collimating and said surface of wafer with a conductive shield member at a potential associated with said potential of said gas plasma.

18. The method of claim 17, further including maintaining said wafer at a potential different from said potential of said gas plasma, and sputtering portions of said film of said material from said wafer to enhance step coverage of said wafer.

19. The method of claim 18, further including achieving said enhanced step coverage by inhibiting pinch off at entry regions of recesses in said surface of said wafer.

20. A kit for modifying an apparatus for sputter deposition of a material on a semiconductor wafer, said apparatus comprising a grounded chamber adapted for creation of a vacuum therein and provided with a supply of an ionizable gas, a negatively-biased target of said material disposed in said chamber, a semiconductor wafer support disposed in said chamber spaced from said target and a collimator interposed between said target and said wafer support, said kit comprising:

an aluminum receiving ring having an anodized exterior surface and including a receiving ring wall portion having a radially inwardly extending receiving ring flange projecting therefrom, said receiving ring wall portion including a plurality of bolt holes therethrough for receiving bolts to secure said receiving ring to a member of said grounded chamber; and

a stainless steel adaptor ring including an adaptor ring annular wall portion having an outer diameter less than an inner diameter of said receiving ring flange and defining a cavity for receiving said collimator therein, said adaptor ring wall portion further having a radially inwardly extending lip at a lower portion thereof and a radially outwardly extending adaptor ring flange projecting therefrom, an outer diameter of said adaptor ring flange being less than a diameter defined by a radially inner surface of said receiving ring wall portion.

21. The kit of claim 20, wherein said adaptor ring includes a plurality of adaptor ring bolt holes extending through said lip, and further including:

an annular shield member having a mounting ring at an upper extent thereof, said mounting ring including tapped mounting ring bolt holes therein alignable with said plurality of adaptor ring bolt holes for securing said shield member to said lip by bolts extending thorough said plurality of adaptor ring bolt holes and into said tapped mounting ring bolt holes; and

a cover ring sized to fit within a diameter defined by an inner surface of said adaptor ring wall portion and over heads of bolts securing said mounting ring to said lip.

22. The kit of claim 20, wherein an anodization layer is present on said exterior surface of said receiving ring and is approximately 6 mils in thickness.

23. The kit of claim 20, wherein said anodized exterior surface of said receiving ring includes bore walls of said plurality of bolt holes.