Attachment or integration of a BIOS device into a computer system using local bus

• US 5,987,551 A
• Filed: 09/30/1997
• Issued: 11/16/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Mei California, Inc. (Micron Technology, Inc.)
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): VO, TIM T
• Application Number:
  US08/940,214
• Time in Patent Office: 777 Days
• Field of Search: 395/750.01, 395/728, 395/821, 395/306, 395/733, 395/288, 395/303, 395/301, 395/302
• US Class Current: 710/315
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Claims

1. A computer comprising:

a central processing unit;

a mezzanine bus;

a BIOS device that is connected to the mezzanine bus; and

core logic connecting the central processing unit to the mezzanine bus comprising;

a state machine for initiating mezzanine bus cycles in a normal mode; and

logic for bypassing the state machine when a BIOS access is initiated;

wherein the core logic is configured such that if a BIOS access is initiated;

the core logic becomes master of the mezzanine bus;

a mezzanine bus cycle in normal mode is not initiated; and

the core logic places the address of the BIOS device on the mezzanine bus.

2. The computer of claim 1, further comprising:

system memory that is connected to the core logic, wherein the core logic controls memory operations involving the central processing unit and the system memory.

3. The computer of claim 1, wherein the mezzanine bus is a PCI bus.

4. The computer of claim 2, wherein the core logic controls BIOS operations involving the central processing unit and the BIOS device on the mezzanine bus by;

receiving data stored in the BIOS device when it is accessed by sampling a portion of the mezzanine bus, and

transferring the data to the central processing unit.

5. The computer of claim 3, wherein the address presented to the BIOS device and the data read from the BIOS device occupy different AD lines on the PCI bus.

6. The computer of claim 4, wherein the core logic sequences a plurality of low-order bits on the BIOS device address so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

7. The computer of claim 5, wherein the control signals used in accessing the BIOS device are passed to the BIOS device over AD lines on the PCI bus.

8. The computer of claim 6, wherein the core logic transfers at least some of the contents of the BIOS device to faster memory at system start-up.

9. The computer of claim 7, wherein a non-volatile, electrically-erasable, programmable read-only memory device contains BIOS instructions.

10. The computer of claim 8, wherein the address presented to the BIOS and the data read from the BIOS device occupy different portions of the mezzanine bus.

11. The computer of claim 9, wherein eight-bit data units are stored in an eighteen-bit address space within the BIOS device.

12. Core logic that controls BIOS operations in a computer system, wherein the BIOS operations involve a central processing unit and a BIOS device on a mezzanine bus, the core logic comprising:

a port for communicating with the central processing unit;

a port for connecting to the mezzanine bus;

logic for initiating mezzanine bus cycles;

logic that bypasses the logic for initiating mezzanine bus cycles when the BIOS device is accessed;

logic that ensures that the core logic is the master of the mezzanine bus;

logic that presents an address to the BIOS device by placing the address on the mezzanine bus;

logic that receives data stored in the BIOS device at the address by sampling a portion of the mezzanine bus; and

logic that transfers the data to the central processing unit.

13. The core logic of claim 12, further comprising logic that sequences a plurality of low-order bits on the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

14. The core logic of claim 12, wherein the mezzanine bus is a PCI bus.

15. The core logic of claim 13, further comprising logic that transfers at least some of the contents of the BIOS device to faster memory at system start-up.

16. The core logic of claim 14, wherein the address presented to the BIOS device and the data read from the BIOS device occupy different AD lines on the PCI bus.

17. Core logic for controlling BIOS operations in a computer system, where the BIOS operations involve a central processing unit and a BIOS device on a mezzanine bus, the core logic comprising:

means for initiating mezzanine bus cycles;

means for bypassing the logic for initiating mezzanine bus cycles when the BIOS device is accessed;

means for ensuring that the core logic is the master of the mezzanine bus;

means for presenting an address to the BIOS device by placing the address on the mezzanine bus;

means for receiving data stored in the BIOS device at the address by sampling a portion of the mezzanine bus; and

means for transferring the data to the central processing unit.

18. The core logic of claim 17, further comprising hardware for sequencing a plurality of low-order bits on the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

19. The core logic of claim 17, wherein the mezzanine bus is a PCI bus.

20. The core logic of claim 18, further comprising means for transferring at least some of the contents of the BIOS device to faster memory at system start-up.

21. The core logic of claim 19, wherein the address presented to the BIOS device and the data read from the BIOS device occupy different AD lines on the PCI bus.