Method and apparatus for a self-timed and self-enabled distributed clock

DC
  • US 5,987,620 A
  • Filed: 11/14/1997
  • Issued: 11/16/1999
  • Est. Priority Date: 09/19/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A self-timed and self-enabled clock circuit for synchronizing operation of a digital circuit, comprising:

  • a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided; and

    a clock delay device, coupled to the control circuit, that has a plurality of inputs and an output that provides an output clock pulse when the clock delay device is enabled, the inputs including;

    a feedback clock input that is coupled to the output of the clock delay device;

    a clock input for receiving the input clock pulses; and

    an enable input that receives the enable signal to enable the clock delay device;

    wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses.

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