Video decompression

• US 5,995,727 A
• Filed: 10/07/1997
• Issued: 11/30/1999
• Est. Priority Date: 07/29/1994
• Status: Expired due to Term

• Current Assignee: Talon Research LLC
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian P., Birch, Nicholas
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/947,677
• Time in Patent Office: 784 Days
• Field of Search: 395/200.77
• US Class Current: 709/247
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Claims

1. An apparatus for synchronizing time in a multiplexed data stream, comprising:

a demultiplexer, accepting a stream of multiplexed data, and outputting a plurality of elementary streams of data, each said elementary stream comprising a series of access units and having a series of time stamps associated therewith;

a clock reference for initializing system time in a first circuit;

a first time counter in communication with said clock reference for keeping system time in a first circuit; and

a second time counter initialized by said clock reference in a second circuit synchronized with said first time counter, for keeping a local copy of said system time and for determining the presentation timing error between said local copy of system time and said system time by comparing said time stamp to said second time counter.

2. The apparatus according to claim 1, wherein said time stamps are presentation time stamps.

3. The apparatus according to claim 1, wherein said time stamps are decode time stamps.

4. An apparatus for synchronizing time in a multiplexed data stream, comprising:

a token source, producing a time-multiplexed stream of tokens, wherein said tokens each comprise a plurality of data words, said data words each including an extension bit which indicates a presence of additional words in said token;

a demultiplexer, accepting a stream of multiplexed data, and outputting a plurality of elementary streams of data, each said elementary stream comprising a series of access units and having a series of time stamps associated therewith;

a first circuit connected to said demultiplexer comprising a first counter;

a second circuit connected to said demultiplexer comprising a second counter;

a third circuit coupled to said first counter and said second counters for initialization of a system time therein, wherein said third circuit is responsive to a SYNC_-- TIME token generated in said token source;

wherein said first counter counts independently of said second counter for maintaining first and second local versions of said system time in said first circuit and said second circuit.

5. The apparatus according to claim 4, wherein said time stamps are presentation time stamps.

6. The apparatus according to claim 4, wherein said time stamps are decode time stamps.

7. The apparatus according to claim 4, further comprising a fourth circuit for correcting said time stamps according to a processing time of said tokens in said second circuit.

8. The apparatus according to claim 4, further comprising a fifth circuit receiving said time stamps, and connected to said first and second counters for producing a signal indicative of whether an access unit has been timely output from said second circuit.

9. An apparatus for synchronizing time in a multiplexed data stream, comprising:

a demultiplexer, accepting a stream of multiplexed data, and outputting a plurality of elementary streams of data, each said elementary stream comprising a series of access units and having a series of time stamps associated therewith;

a clock reference for initializing system time in a first circuit;

a first time counter in communication with said clock reference for keeping system time in a first circuit; and

an elementary stream time counter coupled to said demultiplexer;

a circuit for generating a synchronization time X responsive to said time stamp, said elementary stream time counter, and said first time counter;

a second time counter in a second circuit synchronized with said elementary stream counter, for keeping a local copy of said elementary stream time and for determining the presentation timing error between said local copy of elementary stream time and said synchronization time X.

10. The apparatus according to claim 9, wherein said elementary stream time counter produces a signal indicative of a carry out and said second time counter is reset in response to said signal.

11. The apparatus according to claim 9, wherein said time stamps are presentation time stamps.

12. The apparatus according to claim 9, wherein said time stamps are decode time stamps.

13. The apparatus according to claim 9, further comprising a correction circuit for correcting said time stamps according to a processing time of said tokens in said second circuit.

14. The apparatus according to claim 9, further comprising an early/late-indicator circuit responsive to said synchronized time X and said second time counter for producing a signal indicative of whether an access unit has been timely output from said second circuit.