Method and system for automatically modelling registers for integrated circuit design

• US 5,995,736 A
• Filed: 07/24/1997
• Issued: 11/30/1999
• Est. Priority Date: 07/24/1997
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Sniderman, Bryan S., Aleksic, Milivoje
• Primary Examiner(s): Stamber, Eric W.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US08/899,521
• Time in Patent Office: 859 Days
• Field of Search: 364/578, 364/489, 364/490, 395/500, 395/500.02, 395/500.19
• US Class Current: 716/103
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An integrated circuit modeling system facilitates automatic design of register based hardware devices by generating major pieces of the development outputs from a single input, such as a single register specification source file. The modeling code is kept coherent for all major phases of design and testing. The register specification source file contains all the register information about the device being developed. For example, each register defined in the file contains information about its offset (within its register space), access permissions, size, and field specifications. The system uses a series of associated pre-stored modeling templates in different programming languages, that access the register specification source file and automatically generate behavioral model register code and IC simulation code.

Claims

1. A method for automatically modeling registers for use in integrated circuit design comprising:

storing integrated circuit (IC) register description source data representing organized register data;

automatically generating hardware design simulation code from the register description source data for use in design simulation of the IC;

automatically generating behavioral model register code, representing behavioral characteristics of the IC, from the same register description source data for use in finalizing the IC design.

2. The method of claim 1 wherein the register description source data is a text file.

3. The method of claim 1 further including the step of:

automatically generating register test code for the hardware design simulation code and the behavioral model register code from the register description source data for the purpose of testing the hardware design simulation code and the behavioral model register code.

4. The method of claim 1 wherein the step of automatically generating hardware design simulation code includes storing predefined register templates in a same language as the hardware design simulation code, associating the register description source data to the register templates and automatically populating the associated register templates with appropriate register description source data to automatically create a hardware design simulation register layer.

5. The method of claim 1 wherein the step of automatically generating behavioral model register code includes storing predefined register templates in a same language as the behavioral model register code, associating the register description source data to the register templates and automatically populating the associated register templates with appropriate register description source data to automatically create a behavioral model register layer.

6. The method of claim 1 further including automatically generating documentation from the register description source data source representing configuration information of the register as represented by the description data.

7. The method of claim 1 including the step of generating software headers from the register description source data using a software header template.

8. The method of claim 1 wherein the step of automatically generating behavioral model register code includes forming a register layer based on the IC register description source data and generating a connection file based on the IC register description source data so that the connection file facilitates mapping the register layer to a functional model layer defining the functions for registers in the register layer.

9. The method of claim 8 further including the step of merging register layer data from a current register layer with new register description source data to preserve a previous state of the code and adding only new register data.

10. The method of claim 9 wherein the step of merging further includes:

analyzing updated register description source data;

analyzing existing behavioral model code or existing hardware design simulation code, to obtain data that was in previous register description source data and to determine current register layer connections to the functional model layer;

comparing the updated register description source data to the obtained data and determined current connections; and

generating new model code based on the comparison of the updated register description source data and the obtained data and determined current connections.

11. The method of claim 9 wherein the step of comparing includes comparing data in a current connection file and the updated register description source data and generating a report identifying detected differences.

12. The method of claim 2 wherein the text file contains description data representing register header data and register body data and the register header data includes at least one of the following types of register data:

register name, offset data to a base address of registers in a register class, number of bits in a register, a register type, whether the register is a read, write or read/write type, and whether a register is an indirect register.

13. The method of claim 12 wherein the register body data includes at least one of the following types of field data:

field name, field position, field size, field type, and field attributes.

14. A method for automatically modeling registers for use in integrated circuit design comprising:

storing a single register specification data source representing grouped register data;

automatically generating a behavioral register for the integrated circuit from the single register specification data source and automatically generating a hardware design simulation model from the single register specification data sources wherein an application interface layer and a register model layer is created in a behavioral model register code, and in a different hardware design simulation code, from the same single register specification data source; and

merging register layer data from a current register layer with new register description source data to generate new model code.

15. The method of claim 14 further including the step of automatically generating register test code for the hardware design simulation code and the behavioral model register code from the register description source data.

16. The method of claim 15 further including the step of automatically generating register test code includes the steps of storing register test code templates and generating the register test code using the templates and the register description source data.

17. The method of claim 14 wherein the step of automatically generating a behavioral register model and automatically generating a hardware design simulation model from the same single register specification data source includes the steps of:

storing a first set of predefined register templates containing predefined code in a first programming language for use in generating the behavioral model register code, associating the register description source data to the first set of register templates and automatically populating the associated first set of register templates with appropriate register description source data to automatically create a behavioral model register layer; and

storing a second set of predefined register templates in a second programming language for use in generating the hardware design simulation code, associating the register description source data to the second set of register templates and automatically populating the associated second set of register templates with appropriate register description source data to automatically create a hardware design register layer.

18. The method of claim 17 wherein the first and second set of register templates each include at least a bus decoder template for creating the application interface layer, and a register decoder template operatively associated to a register file template and a connection template to facilitate creation and use of the register layer to interface with a model layer.

19. The method of claim 18 wherein each register file template is operatively associated to a register cell template and the register cell template is operatively associated to a field template.

20. The method of claim 18 wherein the step of merging includes merging register layer data from another previously generated register layer by preserving a previous state of the code and adding only new register data.

21. The method of claim 20 wherein the step of merging further includes:

analyzing updated register description source data;

analyzing existing behavioral model code or existing hardware design simulation code, to obtain data that was in previous register description source data and to determine current register layer connections to the functional model layer;

comparing the updated register description source data to the obtained data and determined current connections; and

generating new model code based on the comparison of the updated register description source data and the obtained data and determined current connections and preserving a previous state of the model code by adding only new register data.

22. A system for automatically modeling registers for use in integrated circuit design comprising:

memory means for storing integrated circuit register description source data representing organized register data and for storing predefined register templates; and

processing means for automatically generating hardware design simulation code from the register description source data and automatically generating behavioral model register code from the same register description source data using the predefined register templates for use in finalizing the IC design.

23. The system of claim 22 wherein the processing means also preserves a previous state of code by deleting only obsolete model code.

24. The system of claim 23 wherein the processing means further includes means for automatically generating register test code for the hardware design simulation code and the behavioral model register code from the register description source data and predefined test templates.