Reconfigurable texture cache

• US 6,002,410 A
• Filed: 08/25/1997
• Issued: 12/14/1999
• Est. Priority Date: 08/25/1997
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: Chromatic Research, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Battle, James T.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/918,226
• Time in Patent Office: 841 Days
• Field of Search: 711/5, 711/170, 711/211, 711/118, 711/127, 711/129, 345/118, 345/147, 345/149, 345/430, 345/507-510, 345/513, 345/515, 345/516
• US Class Current: 345/552
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

A reconfigurable cache in a signal processor provides a cache optimized for texture mapping. In particular, the reconfigurable cache provides two-banks of memory during one mode of operation and a palettized map under a second mode of operation. In one implementation, the reconfigurable cache optimizes mip-mapping by assigning one texture map in one of the memory banks and a second texture map of a different resolution to the other memory bank. A special mapping pattern ("supertiling") between a graphical image to cache lines minimizes cache misses in texture mapping operations.

Claims

1. A reconfigurable cache, comprising;

first and second memory banks each having address terminals for receiving a memory address, and providing an output datum on an output data bus in response to said memory address; and

a multiplexer circuit receiving said memory address of said first memory bank, said output datum of said first memory bank and a control signal, wherein said multiplexer circuit providing said memory address to said address terminals of said second memory bank when said control signal is asserted, and providing said output datum of said first memory bank to said second memory bank, when said control signal is deasserted.

2. A reconfigurable cache as in claim 1, further comprising a second multiplexer circuit receiving and selecting as an output datum of said reconfigurable cache one of said output data from said first and second memory banks.

3. A reconfigurable cache as in claim 1, wherein when said control signal is deasserted, an additional tag bit is examined to determine if said memory address specifies a datum stored in said second memory bank.

4. A reconfigurable cache as in claim 1, wherein said reconfigurable cache is provided as a texture cache used in conjunction with a first texture map and a second texture map, said first and second texture maps being associated with said first and second memory banks.

5. A method for providing a mapping pattern for mapping a graphical image to a cache having a number of cache lines, comprising the steps of:

computing a number of pixels to be held in said cache and a number of pixels in each of said cache lines;

Organizing along a first dimension and a second dimension said pixels in said cache into a square, or a rectangle having an aspect ratio of 2;

1 when said number of pixels in said cache is an odd power of 2;

Organizing along said first and second dimensions said pixels in each cache line in a square or a rectangle having an aspect ratio of 2;

1, when said number of pixels in said cache line is an odd power of 2;

computing the numbers of cache lines along said first and second dimensions of the cache; and

mapping a first group of pixels in said graphical image in accordance with a mapping pattern conforming to said organizations of said cache and said cache lines;

creating a second mapping pattern for said graphical image according to a method comprising the steps of;

(a) taking a copy of said first mapping pattern;

(b) splitting said first mapping pattern into two halves along first dimension;

(c) forming a new mapping pattern by exchanging said two halves; and

(d)combining said first mapping pattern with said new mapping pattern along the second dimension to form a third mapping pattern; and

tiling said graphical image according with said third mapping pattern.

6. A method for providing a texture cache for supporting accesses to a first texture map and a second texture map, each texel in each texture map having a texel address, said method comprising the steps of:

providing said texture cache as a first and second sets of addressable memory locations, wherein the address of each memory location in said first set of memory location is distinguishable from the address of a corresponding memory location by the value of a selected address bit;

assigning, as an index, to said first texture map a binary value and to said second texture the complement of said binary value;

using as an address to said texture cache the combination of said index and said texel address, assigning to said selected address bit said index, thereby mapping texels in said first texture Map to said first set of addressable memory locations and texels in said second texture map to said second said of addressable memory locations.

7. A method as in claim 6, wherein said texture cache comprises a first memory bank and a second memory bank, said first set of memory locations being provided in said first memory bank and said second set of memory locations being provided in said second memory bank.

8. A method as in claim 6, wherein said binary value is the least significant bit of the value of a level of detail index, said values of said level of detail index being integer values assigned consecutively to texture maps of successively greater apparent distances.