Integrated video and memory controller with data processing and graphical processing capabilities

• US 6,002,411 A
• Filed: 11/16/1994
• Issued: 12/14/1999
• Est. Priority Date: 11/16/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Interactive Silicon, Inc.
• Inventors: Dye, Thomas Anthony
• Primary Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/340,667
• Time in Patent Office: 1,854 Days
• Field of Search: 345/112-115, 345/118-120, 345/153, 345/155, 345/501-504, 345/507, 345/512, 345/520, 345/521, 345/526, 345/418, 345/522, 345/186, 345/509, 345/202, 395/501, 395/503, 395/504, 395/507, 395/512, 395/520, 395/521, 395/526, 711/1, 711/6, 711/100, 711/104, 711/105, 711/147, 711/148, 711/153, 711/170, 711/173
• US Class Current: 345/542
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

An integrated memory controller (IMC) which incorporates novel memory, graphics, and audio processing capabilities in a single logical unit. The IMC includes numerous significant advances which provide greatly increased performance over prior art systems. The integrated memory controller (IMC) includes one or more symmetric memory ports for connecting to system memory. The IMC also includes video outputs, preferably RGB (red, green, blue) outputs as well as horizontal and vertical synchronization signal outputs, to directly drive the video display monitor. The IMC transfers data between the system bus and system memory and also transfers data between the system memory and the video display output, thereby eliminating the need for a separate graphics subsystem. The IMC also improves overall system performance and response using main system memory for graphical information and storage. The IMC system level architecture reduces data bandwidth requirements for graphical display data since the host CPU is not required to move data between main memory and the graphics subsystem as in conventional computers, but rather the graphical data resides in the same subsystem as the main memory. Therefore the host CPU or DMA master is not limited by the available bus bandwidth. The IMC includes compression and decompression engines for compressing and decompressing data within the system. The IMC also includes a novel pointer-based display list architecture which includes windows workspace areas spaces which define the format of the data and the data type to read or written.

Claims

1. A computer system including a memory controller which performs memory control and video functions, comprising:

a CPU;

a memory controller coupled to said CPU which performs system memory control and video functions, wherein the memory controller includes one or more video ports for providing video signals;

system memory coupled to said memory controller, wherein said system memory stores video data and non-video data; and

a display device coupled to said one or more video ports of said memory controller, wherein said memory controller accesses said video data in said system memory and provides video signals through said one or more video ports to said display device;

wherein said memory controller receives non-video data from said CPU and stores said non-video data in said system memory and wherein said memory controller transfers said non-video data from said system memory to said CPU on CPU request;

wherein said memory controller includes a compression/decompression engine, wherein said compression/decompression engine is operable to compress received data and store said compressed data in said system memory, and wherein said compression/decompression engine is operable to receive data from said system memory and decompress said data received from said system memory; and

wherein said compression/decompression engine is operable to compress/decompress both said video data and said non-video data being transferred to/from said system memory.

2. The computer system of claim 1, wherein said memory controller includes one or more video ports for providing video signals directly to said display device.

3. The computer system of claim 2,

wherein said system memory comprises a plurality of memory locations, wherein said system memory is operable to store said video data in any of said memory locations.

4. The computer system of claim 3, wherein said system memory comprises a single type of memory, wherein said single type of memory stores said video data and said non-video data.

5. The computer system of claim 1, wherein said memory controller includes an interface to the system memory, wherein the memory controller is operable to access both said video data and non-video data from said system memory.

6. The computer system of claim 1, wherein said CPU provides video instructions to said memory controller;

wherein in response to said video instructions said memory controller reads portions of said video data and provides said video signals to said display device.

7. The computer system of claim 1, wherein said non-video data includes code and data used by said CPU for executing one or more applications.

8. The computer system of claim 1, wherein said memory controller performs audio functions and generates audio signals, the computer system further comprising:

one or more speakers coupled to said memory controller which receives said audio signals and generates sound in response to said audio signals.

9. The computer system of claim 8, further comprising:

an audio digital to analog converter coupled between said memory controller and said one or more speakers which receives said audio signals from said memory controller and generates signals to said one or more speakers.

10. The computer system of claim 1, wherein said computer system includes a bus coupled between said CPU and said memory controller;

wherein said memory controller comprises;

a bus interface coupled to said bus;

a graphics engine coupled to said bus interface;

one or more memory control units coupled to said graphics engine and also coupled to said system memory;

a window assembler coupled to said one or more memory control units;

a display storage buffer coupled to said video assembly unit for storing video data; and

one or more video output ports coupled to said window assembler for transferring said video data to said display device.

11. The computer system of claim 10, wherein said memory controller further includes:

one or more digital to analog converters coupled between said display storage buffer and said one or more video outputs for converting said video data to analog signals, wherein said analog signals are provided as outputs on said one or more video output ports.

12. The computer system of claim 11, wherein said CPU provides video instructions to said memory controller, wherein said memory controller further includes:

an execution engine coupled between said bus interface logic and said graphics engine, wherein said execution engine processes instructions from said CPU for manipulation of data in said system memory.

13. The computer system of claim 1, wherein said compression/decompression engine is further operable to receive data from said system memory and compress said data received from said system memory, and wherein said compression/decompression engine is further operable to decompress received data and store said decompressed data in said system memory.

14. The computer system of claim 1, further comprising:

a non-volatile storage subsystem coupled to said memory controller, wherein said memory controller transfers data between said non-volatile storage subsystem and said system memory.

15. The computer system of claim 14, wherein said compression/decompression engine is further operable to compress/decompress data transferred between said non-volatile storage subsystem and said system memory.

16. A memory controller for performing memory control and video functions, comprising:

one or more memory control units adapted for coupling to a system memory for controlling functions of the system memory;

a graphics engine coupled to the one or more memory control units for performing graphics operations on data; and

one or more video ports coupled to the graphics engine and coupled to the one or more memory control units for providing video signals to a display device; and

a compression/decompression engine, wherein said compression/decompression engine is operable to compress received data and store said compressed data in said system memory, and wherein said compression/decompression engine is operable to receive data from said system memory and decompress said data received from said system memory; and

wherein said compression/decompression engine is operable to compress/decompress both said video data and said non-video data being transferred to/from said system memory.

17. The memory controller of claim 16,

wherein the one or more memory control units are adapted for accessing video data to/from the system memory, and wherein the one or more memory control units are operable to receive video data and non-video data from a CPU and store the video data and non-video data from the CPU in the system memory.

18. The memory controller of claim 16, wherein said one or more video ports are adapted for providing the video signals directly to the display device.

19. The computer system of claim 16, wherein the system memory comprises a plurality of memory locations, wherein said system memory is operable to store said video data in any of said memory locations;

wherein said one or more memory control units are adapted for accessing video data from any location in the system memory.

20. The computer system of claim 16, wherein said one or more memory control units are adapted for accessing a single type of memory, wherein said single type of memory stores said video data and said non-video data.

21. The memory controller of claim 16, wherein the memory controller is adapted to receive video instructions from the CPU;

wherein in response to said video instructions said memory controller is operable to read video data from the system memory and provide the video signals to the display device.

22. The memory controller of claim 16, wherein the system memory stores code and data useable by a CPU for executing one or more applications;

and

wherein the memory controller is operable to transfer non-video data from the system memory to the CPU on CPU request.

23. The memory controller of claim 16, wherein said memory controller further comprises:

a bus interface for coupling to a bus;

wherein said graphics engine is coupled to said bus interface;

a window assembler coupled to said one or more memory control units;

a display storage buffer coupled to said window assembler for storing video data; and

wherein said one or more video ports are coupled to said window assembler for transferring said video data to the display device.

24. The memory controller of claim 23, wherein said memory controller further includes:

one or more digital to analog converters coupled between said display storage buffer and said one or more video ports for converting said video data to analog signals, wherein said analog signals are provided as outputs on said one or more video ports.

25. The memory controller of claim 23, wherein the memory controller is adapted to receive video instructions from the CPU;

wherein said memory controller further includes;

an execution engine coupled between said bus interface logic and said graphics engine, wherein said execution engine processes instructions received from the CPU for manipulation of data in the system memory.

26. The memory controller of claim 16, wherein said compression/decompression engine is further operable to receive data from said system memory and compress said data received from said system memory, and wherein said compression/decompression engine is further operable to decompress received data and store said decompressed data in said system memory.