Network connector operable in bridge mode and bypass mode

• US 6,006,275 A
• Filed: 10/06/1998
• Issued: 12/21/1999
• Est. Priority Date: 05/12/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Zager, Robert P., Picazo, Jose J. Jr., Lee, Paul Kakul
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/167,306
• Time in Patent Office: 441 Days
• Field of Search: 709/220-226, 709/249-253, 370/351, 370/401, 370/404, 370/406
• US Class Current: 709/249
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 12/4616 LAN interconnection over a LAN backbone
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/046 comprising network management agents or mobile agents therefor
• CPC Class Codes: H04L 41/26 using dedicated tools for LAN [Local Area Network] management
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 63/0209 Architectural arrangements, e.g. perimeter networks or demilitarized zones
• CPC Class Codes: H04L 63/083 using passwords cryptographic mechanisms or cryptographic arrangements for entity authentication using a predetermined code H04L9/3226
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor. The main processor is coupled to another port of the memory and analyzes received packets for bridging to other LAN segments or forwarding to an SNMP agent. The main microprocessor and the Ethernet processor coordinate to manage the utilization of storage locations in the shared memory. Another port is coupled to an uplink interface to higher speed backbone media such as FDDI, ATM etc. Speeds up to media rate are achieved by only moving pointers to packets around in memory as opposed to the data of the packets itself. A double password security feature is also implemented in some embodiments to prevent accidental or intentional tampering with system configuration settings.

Claims

1. In a computer system having a first network and a second network, a device for connecting the first network with the second network, said device comprising:

an integrated bridge and hub operable in a first mode and a second mode, said integrated bridge and hub connectable between the first network and the second network; and

a controller for controlling said integrated bridge and hub operating in either of said first mode and said second mode, such that when said integrated bridge and hub is operating in said first mode said integrated bridge and hub operates as a bridge between the first network and the second network, and when said integrated bridge and hub is operating in said second mode said integrated bridge and hub operates as a hub between said first network and said second network and unifies the first network and the second network.

2. The device as recited in claim 1, wherein said controller includes a repeater.

3. The device as recited in claim 2, and further comprising a microprocessor coupled to said controller.

4. The device as recited in claim 3, and further comprising memory shared by both said microprocessor and said controller.

5. A device comprising:

a connector for connecting a first network with a second network, said connector operable in a bridge mode and a hub mode, such that when said connector is operating in said hub mode, said connector unifies the first network with said second network; and

a housing for housing connector.

6. The device as recited in claim 5, wherein said connector includes processor for controlling said connector in operating in either of said bridge mode and said hub mode.

7. The device as recited in claim 6, wherein said connector includes memory connected to said processor.

8. The device as recited in claim 6, wherein said connector includes a repeater/controller having a plurality of repeater ports.